Data storage device, storage medium controller and control method

Abstract

The invention discloses a data storage device, a storage medium controller and a control method. According to the storage medium control method, a storage medium receives a plurality data triggering signals having different phase displacement under write-in leveling operation in time sharing to be compared with a frequency signal and output a data signal based on the comparison. Under the write-in leveling operation, the condition that the data triggering signals and the frequency signal are synchronously transmitted to the storage medium causes a data signal to be subjected to a transition event. The method includes counting the abovementioned transition event. If counting statistics show that the abovementioned transition event occurs only once in a whole round of transformation tests of the abovementioned phase displacement, the method adopts phase displacement corresponding to the transition event to form a first data triggering signal which is received by the storage medium and is captured as data of write-in operation for reference. The invention can prevent write-in errors caused by desynchrony of the frequency signal and data triggering signals at the storage medium end.

Description

technical field [0001] The invention relates to a data storage device, a storage medium controller and a control method. Background technique [0002] In addition to using frequency signals (such as DDR's CK signal) and data signals (such as DDR's DQ signal), the reading and writing of high data rate storage media (for example, double data rate synchronous dynamic random access memory, DDR), Usually also refer to the data trigger signal (such as the DQS signal of DDR). Wherein, the above-mentioned CK signal may be CK and CK# signals in differential form; the above-mentioned DQS signal may be DQS and DQS# signals in differential form. [0003] figure 1 It shows waveforms of signals applied to the write operation of the storage medium, including: a clock signal CK, a data trigger signal DQS, and a data signal DQ. According to the clock signal CK and the synchronous trigger point Ts of the data trigger signal DQS, the data on the data signal DQ is captured and written into t...

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Problems solved by technology

[0004] However, as the data rate increases, the length difference between the leads of the frequency signal CK and the data trigger signal DQS on the motherboard will seriously affect the synchronization of the two signals

In particular, when the synchronous trigger point observed between the frequency signal CK and the data trigger signal DQS is not indeed a synchronous trigger event, it will result in asynchronous input to the storage medium, resulting in an error in the write operation

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