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H-bridge pfc circuit and the falling edge sampling method of the inductor current in the circuit

A circuit and inductance technology, applied in the field of communication, can solve problems such as affecting the reliability and stability of products, causing great harm, and not proposing solutions, so as to achieve the effect of improving sampling fidelity and reducing costs.

Active Publication Date: 2017-03-15
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, at such a small duty cycle, the inductor current flowing through the MOS tube not only includes the actual inductor current, but also includes a large reverse current. Therefore, the current signal sampled at this time is higher than the actual inductor current. Large signal, resulting in sampling distortion
[0015] In addition, due to the delay in sampling, calculation, control, and hardware response in the PFC circuit, the delay in this circuit will cause sampling distortion when the duty cycle is small, that is, the actual inductor current is large, but due to the delay in sampling, the sampling obtained The current signal is zero or very small, the harm caused by this sampling distortion is particularly great
[0016] To sum up, in the H-bridge PFC circuit, if only the rising edge of the inductor current is used for loop control, the above-mentioned problem of sampling distortion at a small duty cycle will occur. This sampling distortion will be amplified through the transfer of the control loop, which will cause Greatly affect the reliability and stability of the product
[0017] For the above-mentioned problems in related technologies, no effective solution has been proposed yet

Method used

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  • H-bridge pfc circuit and the falling edge sampling method of the inductor current in the circuit
  • H-bridge pfc circuit and the falling edge sampling method of the inductor current in the circuit
  • H-bridge pfc circuit and the falling edge sampling method of the inductor current in the circuit

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Embodiment 1

[0049] Figure 8 It is a schematic circuit diagram of an H-bridge PFC circuit according to an embodiment of the present invention. Such as Figure 8 As shown, the circuit includes: a first series circuit composed of MOS transistors (S1, S2) connected in series, a second series circuit composed of two step-up diodes (D1, D3) connected in series, and two serial circuits connected in series The third series circuit composed of flow diodes (D2, D4), the output BUS capacitor C B , inductance L 1 and load R L , wherein, the first series circuit, the second series circuit, the third series circuit, the capacitor C B and the load R L connected in parallel with each other to form a parallel circuit, the inductance L 1 and the load R L In series with the parallel circuit, in the circuit, it also includes: a current transformer CT, one end of which is coupled to the inductance, and the other end is coupled to the connection between the two boost diodes (D1, D3) connected in series...

Embodiment 2

[0063] In this embodiment, a falling edge sampling method of the inductor current in the H-bridge PFC circuit is provided, wherein the H-bridge PFC circuit includes: a current transformer and an inductor, wherein one end of the current transformer is connected to the Inductive coupling connection, the other end is coupled and connected to the line between the two boost diodes connected in series; this method is based on the above-mentioned H-bridge PFC circuit, and the specific structure of the circuit described in this implementation can be referred to the above-mentioned embodiment, which will not be described here Let me repeat. Figure 15 It is a flowchart of a falling edge sampling method of an inductor current in an H-bridge PFC circuit according to an embodiment of the present invention. Such as Figure 15 As shown, the method includes:

[0064] Step S1502, the current transformer acquires the current signal flowing through the inductor;

[0065] Step S1504, the curr...

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Abstract

The invention discloses an H-bridge PFC circuit and a method for sampling the falling edge of the inductance current in the circuit, wherein the above-mentioned H-bridge PFC circuit comprises: a first series circuit composed of MOS transistors connected in series, and two booster circuits connected in series A second series circuit composed of diodes, a third series circuit composed of two freewheeling diodes connected in series, an output BUS capacitor, an inductor and a load, wherein the first series circuit, the second series circuit, the third series circuit, the capacitor and The loads are connected in parallel to each other to form a parallel circuit, and the inductor and the load are connected in series with the parallel circuit; one end of the current transformer is coupled to the inductor, and the other end is coupled to the line between the two boost diodes connected in series. The above-mentioned technical solution provided by the present invention improves the fidelity effect of sampling the inductor current when there is a small duty cycle for sampling the rising edge in the H-bridge PFC circuit, and reduces the cost.

Description

technical field [0001] The invention relates to the communication field, in particular to an H-bridge PFC circuit and a falling-edge sampling method of an inductor current in the circuit. Background technique [0002] High efficiency, high power density and low cost have become three important indicators pursued by communication power supplies. In order to meet these three goals, the circuit topology of PFC has changed from traditional bridge, double boost (BOOST) bridgeless power factor correction (Power FactorCorrection (referred to as PFC), H-bridge PFC and interleaved parallel technologies of various topologies are constantly developing. [0003] In order to improve efficiency, dual BOOST bridgeless PFC is widely used, and its circuit schematic diagram is as follows figure 1 shown. figure 1 It consists of two PFC circuits. In the positive half cycle of the power frequency, the inductor L1, the boost diode D1 and the MOS tube S1 form a BOOST circuit to work; in the neg...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02M1/42
CPCH02M1/4225H02M3/1584Y02B70/10H02M1/0009H02M1/0085
Inventor 刘玮罗勇金亮亮
Owner ZTE CORP