Semiconductor device

Abstract

A semiconductor device comprising: a p-type semiconductor substrate; an n-type embedded layer disposed on the semiconductor substrate; and a p-type embedded layer disposed on the embedded layer. The back gate layer; the drain layer arranged on the above back gate layer and having an n-type conductivity; the source layer arranged on the above back gate layer and separated from the drain layer and having an n-type conductivity; on the above back gate layer a gate electrode provided in a region directly above a portion of the gate layer between the drain layer and the source layer; and a drain electrode in contact with a part of the upper surface of the drain layer. A thickness of the drain layer in a region directly below a contact surface between the drain layer and the drain electrode is half of a total thickness of the back gate layer and the drain layer in a region directly below the contact surface.

Description

[0001] cross reference [0002] This application claims priority based on Japanese application No. 2012-005127 filed on January 13, 2012, and uses the entire content for this specification. technical field [0003] Embodiments described below generally relate to semiconductor devices. Background technique [0004] In the past, in the lateral DMOS (Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor: double-diffused metal-oxide-semiconductor field-effect transistor), the drain layer was divided into a drift layer that mainly flows current, and a layer that mainly ensures voltage resistance. Drain buffer layer. Furthermore, since these are independently controlled, it is difficult to achieve both improvement in withstand voltage and improvement in current capability per unit area. In addition, when only the drift layer is provided without providing the drain buffer layer, it is difficult to improve the withstand voltage, and there is a problem that the device a...

AI Technical Summary

Problems solved by technology

Moreover, since they are independently controlled, it is difficult to balance the improvement of the withstand voltage and the improvement of the current capacity per unit area.

In addition, when only the drift layer is provided without the drain buffer layer, it is difficult to improve the withstand voltage, and when the required withstand voltage is ensured, there is a problem that the device area becomes larger.

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