Microprocessor instruction processing method and system based on single/double launch instruction set

Abstract

The invention relates to a microprocessor instruction processing method and system based on a single / dual transmitting instruction set. The processing method comprises the following steps of reading an instruction from a memory according to the address of the instruction, and the instruction comprises a marking position indicating the instruction to be a single transmitting instruction or a dual transmitting instruction; carrying out decoding on the read instruction, obtaining a decoding result of the marking position, an operating code and an operating number, and according to the marking position, determining the instruction to be the single transmitting instruction or the dual transmitting instruction; if the instruction is determined to be the single transmitting instruction, finishing the operation of the single transmitting instruction in a first assembly line, if the instruction is determined to be the dual transmitting instruction, finishing the first operation in the dual transmitting instruction in the first assembly line, finishing the second operation of the dual transmitting instruction in a second assembly line, and the first assembly line and the second assembly line operate in parallel in the same manner; and writing the operation results of the first assembly line and the second assembly line back to a register.

Description

technical field [0001] The invention relates to a microprocessor instruction processing method and system, in particular to a microprocessor instruction processing method and system based on a mixed single-issue / double-issue instruction set. Background technique [0002] In the basic architecture of a microprocessor, the instruction processing process executed in one instruction cycle mainly includes steps such as instruction addressing, instruction reading, instruction decoding, operand reading, operation, and result writing back. Traditional single-issue instruction-based microprocessors perform only one operation during the processing of an instruction. Although in fact many operations can be processed in parallel, it cannot be realized due to the limitation that the operation unit ALU can only perform one operation in one cycle, so the ALU has become the bottleneck of the efficiency of traditional microprocessors, making this traditional single-issue instruction-based M...

AI Technical Summary

Problems solved by technology

This method makes the hardware structure of the microprocessor relatively simple, but the software programming is very complicated.

Since the single-issue / double-issue instructions are not dynamically switched, but need to modify the state of the microprocessor to use two different sets of logic to process the single-issue and double-issue instructions, it is necessary to explicitly tell the microprocessor the next Whether the instruction is a single-issue instruction or a dual-issue instruction, this greatly increases the programming complexity of the microprocessor

And because the single-issue instruction and the dual-issue instruction are all sets, that is, to realize all the functions of the microprocessor respectively, both pipelines must implement all instructions, that is to say, all operations must be repeated twice.

Moreover, due to the huge number of instructions, the instruction encoding (operation code) field is very long, which compresses the space of other fields such as the address field and the immediate field, which limits the performance of the microprocessor in other aspects

For example, a typical ARM microprocessor takes up a large space for the instruction field, resulting in a reduction in the register field, so that the register depth can only support 16 bits.

[0007] It can be seen that the difficulty in balancing performance and cost / power consumption is a key limitation of traditional microprocessors

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