high-speed storage device
A high-speed storage and circuit technology, applied in the direction of input/output to record carrier, etc., can solve the problem of low real-time storage performance, and achieve the effect of low power consumption and speed improvement
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specific Embodiment approach 1
[0017] Specific implementation mode one: combine figure 1 Describe the present embodiment, the high-speed storage device described in the present embodiment, it comprises FIFO circuit 1, FPGA circuit 2, hard disk 3, AVR single-chip microcomputer 4 and USB circuit 5;
[0018] The data signal output end of FIFO circuit 1 is connected with the image data signal input end of FPGA circuit 2, and the USB serial data port of FPGA circuit 2, the USB serial data port of hard disk 3 are all connected with the serial port of USB circuit 5,
[0019] The control signal output end of FPGA circuit 2 is connected with the control signal input end of AVR single-chip microcomputer 4, and the USB serial data port of AVR single-chip microcomputer 4 is connected with the serial data port of USB circuit 5.
[0020] The AVR circuit is equivalent to a central controller to complete various underlying scheduling tasks;
[0021] The USB circuit mainly completes the communication with the upper compute...
specific Embodiment approach 2
[0023] Specific implementation mode two: combination figure 2 Describe this embodiment, this embodiment is a further limitation on the high-speed storage device described in the first specific embodiment,
[0024] Described FPGA circuit 2 comprises data latch, CRC check module, data buffer module, FIFO read interface logic module, ATA interface logic module and data selector;
[0025] The data latch is used to latch the received data and wait for storage;
[0026] The CRC verification module is used to perform CRC verification on the data output by the data latch according to the set bit error rate of the data storage, generate CRC verification data and send it to the data selector;
[0027] The data buffer module works synchronously with the CRC check module, and sends the data output by the data latch to the data selector;
[0028] The data selector is used to determine the data format of the synchronous combination of the latched FIFO data and the CRC check data by the d...
specific Embodiment approach 3
[0032] Embodiment 3: This embodiment is a further limitation of the high-speed storage device described in Embodiment 1.
[0033] The USB circuit 5 is realized by using the chip TUSB6250.
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