Clock sampling self-adaption adjusting method and clock sampling self-adaption adjusting system

Abstract

The invention discloses a clock sampling self-adaption adjusting method comprises the following steps: input data are subjected to time delay operation and sampling operation respectively by main and standby monitoring devices according to preset initial time-delay amounts; in a time window, the initial time-delay amounts are adjusted; every time when the initial time-delay amounts are adjusted, main and standby sampling result sequences formed by sampling output values which are obtained after the input data are sampled by the main and standby monitoring devices are output to a time-delay amount adjusting device; the time-delay amount adjusting device controls switch of the main and standby monitoring devices according to the main and standby sampling result sequences, and time-delay amounts are respectively configured for the switched main and standby monitoring devices. The invention also provides a corresponding system. The method and the system provided by the invention are characterized in that data are monitored by the main and standby monitoring devices, switch between the main and standby monitoring devices can be utilized when time delay changes quickly, a time sequence can be recovered to a normal interval in a correct and fast manner, a transmission passageway does not need to be occupied, and transmission efficiency cannot be affected.

Description

technical field [0001] The invention relates to the technical field of digital device interfaces, in particular to a method and system for self-adaptive adjustment of clock sampling. Background technique [0002] In a digital system, the reception of digital signals between devices often adopts the way of clock edge sampling. This method requires a certain timing relationship between the clock edge and the data to ensure the correctness and stability of the sampling. The usual method is to measure the static relative delay between the data link and the clock during development. According to this delay It can adjust the delay of the data or clock at the output or input. However, in this way, in a system with a low sampling rate, due to the large timing margin, the timing changes caused by environmental changes such as temperature and humidity often have no impact on the interface timing, so it will not affect the correctness of the interface. However, in modern communicatio...

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Problems solved by technology

However, since the training sequence occupies the transmission channel, it will affect the transmission efficiency and has a certain lag

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