A method of manufacturing an array substrate

Abstract

The invention discloses a manufacturing method of an array substrate, which relates to the field of display technology and is designed to simplify the manufacturing process while ensuring the etching quality. The manufacturing method comprises: sequentially forming a shielding layer, a buffer insulating layer, an active Layer, gate insulating layer, NMOS gate in the display area and the drive area; form the PMOS gate in the drive area on the aforementioned substrate, the NMOS gate and the PMOS gate are on the same layer, and are formed in the common electrode connection area at the same time The first via hole is used to connect the shielding layer and the source-drain electrode layer; an intermediate insulating layer is formed on the aforementioned substrate, and the second via hole in the common electrode connection area and the display area and the driving area are formed In the third via hole, the second via hole is in the same position as the first via hole for connecting the shielding layer and the source-drain electrode layer, and the third via hole is used for connecting the active layer and the source-drain electrode layer layer; forming a source-drain electrode layer on the aforementioned substrate. The invention is applicable to the manufacturing process of the array substrate.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a method for manufacturing an array substrate. Background technique [0002] With the development of low-temperature polysilicon technology, high PPI (PixelPerInch, the number of pixels per inch) products have gradually become the mainstream. The disadvantage of high PPI products is the reduction of storage capacitor area, so additional storage capacitors are required. To compensate for the reduction in the area of ​​the storage capacitor itself, the corresponding countermeasures are mostly to increase the shielding layer at the bottom layer, and the shielding layer is connected to the common electrode, so that the storage capacitance between the shielding layer and the active layer is increased to compensate for the reduction in the storage capacitance itself . [0003] The planar structure of the low-temperature polysilicon array substrate is as follows: Figure 1a As...

AI Technical Summary

Problems solved by technology

If the process is simplified and a patterning process is applied to the above two via holes, since the depth of the via hole used to connect the source-drain electrode layer and the active layer is different from the depth of the via hole used to connect the shielding layer and the source-drain electrode layer, the required The etching time is also different, so the via hole used to connect the source-drain electrode layer and the active layer is over-etched, and the via hole used to connect the shielding layer and the source-drain electrode layer is not etched in place

Images