A kind of cmos transistor and its manufacturing method

A manufacturing method and technology for transistors, which are applied in the fields of transistors, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of complex low-temperature polysilicon process and high cost of display devices, and achieve the effect of saving manufacturing costs and reducing patterning processes.

Active Publication Date: 2015-08-19
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The invention solves the technical problems of complex low-temperature polysilicon process and high cost of display devices based on low-temperature polysilicon process in the prior art

Method used

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  • A kind of cmos transistor and its manufacturing method
  • A kind of cmos transistor and its manufacturing method
  • A kind of cmos transistor and its manufacturing method

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Experimental program
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Embodiment 1

[0044] Such as figure 1 As shown, this embodiment provides a method for manufacturing a CMOS transistor, including forming a channel, a gate electrode, an ohmic contact layer, and source and drain electrodes on a substrate; wherein the step of forming the channel includes:

[0045] S1. The thickness deposited on the substrate 1 is The amorphous silicon layer 3, and then take a dehydrogenation process for the amorphous silicon, and crystallize the amorphous silicon layer to form a polysilicon layer 3 through processes such as laser irradiation, and the substrate can be a substrate such as transparent glass or quartz;

[0046] S2. If image 3 As shown, the polysilicon layer is etched to form an N channel region and a P channel region; a photoresist semi-retained region is formed corresponding to the N channel region through a patterning process, and a photoresist semi-retained region is formed corresponding to the P channel region. The track area forms a photoresist fully res...

Embodiment 2

[0062] This embodiment provides a method for manufacturing a low-temperature polysilicon CMOS (complementary metal oxide semiconductor) device array substrate and a TFT-LCD (thin film field-effect transistor LCD) array substrate, which includes the method for manufacturing a CMOS transistor described in Embodiment 1 ,Also includes:

[0063] S10. Deposit thickness by PECVD method is about passivation layer 12, and forming via holes in the passivation layer;

[0064] S11. Deposit a layer thickness of about The transparent conductive layer 13, the transparent conductive layer is generally ITO or IZO, and can also be other metals and metal oxides; the transparent pixel electrode is formed by one photolithography, and its cross-sectional view is as follows Figure 10 shown.

Embodiment 3

[0066] This embodiment also provides a CMOS transistor produced by the above manufacturing method, including a substrate and a channel formed on the substrate, a gate electrode, an ohmic contact layer, and source and drain electrodes; wherein the channel is included in the polysilicon layer Form the N channel region, the photoresist semi-retained region corresponding to the N channel region, the photoresist full reserve region corresponding to the P channel region and the P channel region by one patterning; Removing the photoresist and partially removing the photoresist in the photoresist fully reserved area, implanting phosphorus atoms into the N channel area to form an N channel; Boron atoms are implanted into the channel region to form a P channel.

[0067] The manufacturing process of the CMOS transistor described in this embodiment is simple and stable in performance, and more complex array substrates can be fabricated on this basis.

[0068] Optionally, a gate oxide lay...

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Abstract

The invention discloses a manufacture method of a CMOS (complementary metal-oxide-semiconductor transistor) transistor. The manufacture method comprises the steps of forming a channel, a gate electrode, an ohmic contact layer, a source electrode and a drain electrode on a substrate, wherein the step of forming the channel comprises the steps of: S1, depositing an amorphous silicon layer on the substrate, and then crystallizing the amorphous silicon layer into a polysilicon layer; S2, etching the polysilicon layer to form an N-type channel region and a P-type channel region; forming a photoresist semi-conservation area correspondingly to the N-channel region by a one-off primary composition technique, and forming a photoresist full-conservation area correspondingly to the P-type channel region; S3, removing the photoresist of the photoresist semi-conservation area by an ashing process and conserving a part of photoresist of the photoresist full-conservation area, injecting phosphorus atoms by an ion injection mode, and forming an N channel, and S4, stripping and removing the photoresist on the surface of the P-type channel region by a wet process or a dry method, and injecting boron atoms into the P channel. According to the manufacture method, the complexity of a low-temperature polysilicon process and the manufacture cost are reduced.

Description

technical field [0001] The invention relates to the field of low-temperature polysilicon display, in particular to a polysilicon channel doping process, and in particular to a low-temperature polysilicon CMOS transistor and a manufacturing method thereof. Background technique [0002] For traditional amorphous silicon LCD displays, the driver IC and the glass substrate are separate designs that cannot be integrated. Therefore, a large number of connectors are required between the driver IC and the glass substrate. Generally speaking, an amorphous silicon LCD panel requires about 4,000 connectors, which inevitably leads to a complex structure, high module manufacturing costs, and poor stability of the panel, resulting in a relatively high failure rate. . Furthermore, the separate design of the driver IC and the glass substrate also makes it difficult for the LCD to achieve further thinning, which is a big blow to thin and light notebook computers and tablet PCs. In contrast...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L21/77H01L27/092
Inventor 孙冰
Owner BOE TECH GRP CO LTD
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