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Semiconductor process, semiconductor structure and its packaging structure

A semiconductor and process technology, applied in the semiconductor process field with button-shaped bumps, can solve the problems of general products without structure, solder overflow, inconvenience, etc.

Active Publication Date: 2017-04-12
CHIPBOND TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The existing conventional semiconductor packaging structure has a substrate, a chip and solder, wherein the conventional semiconductor packaging structure uses solder to electrically bond the bumps of the chip to the connection pads of the substrate. However, due to the increasing volume of current electronic products, The smaller the pitch, the smaller the pitch of the bumps on the chip. In this case, the solder is likely to overflow to the adjacent bumps during reflow and cause a short circuit, which affects the authenticity rate of the product.
[0003] It can be seen that the above-mentioned existing semiconductor technology obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.
In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above-mentioned problems. This is obviously related. The problem that the industry is eager to solve

Method used

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  • Semiconductor process, semiconductor structure and its packaging structure
  • Semiconductor process, semiconductor structure and its packaging structure
  • Semiconductor process, semiconductor structure and its packaging structure

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Embodiment Construction

[0062] In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation and structure of the semiconductor process, semiconductor structure and packaging structure proposed by the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. , features and their effects are described in detail below.

[0063] see figure 1 and Figure 2A to Figure 2H , a preferred embodiment of the present invention, a semiconductor process comprises the following steps: first, please refer to figure 1 and Figure 2A , providing a carrier 110, the carrier 110 has a surface 111 and a metal layer A formed on the surface 111, the metal layer A has a plurality of substrate regions A1 and a plurality of outer regions A2 located outside the substrate region A1; then, see figure 1 and Figure 2B , forming a first photoresist layer P1 on the metal l...

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Abstract

The invention relates to a semiconductor technology, a semiconductor structure and a package structure thereof. The semiconductor technology comprises the following steps: providing a carrier, wherein the carrier has a metal layer, and the metal layer has a plurality of substrate areas and a plurality of lateral areas; forming a first photoresist layer; forming a plurality of bearing parts; removing the first photoresist layer to expose the bearing parts, wherein each bearing part has a bearing surface, and each bearing surface has a first area and a second area; forming a second photoresist layer which exposes the first areas of the bearing surfaces; forming a plurality of joint parts, wherein the joint parts cover the first areas of the bearing surfaces so that the joint parts are enabled to be connected with the bearing parts to form snap bumps; removing the second photoresist layer to expose the snap bumps; and removing the lateral areas of the metal layer to enable a plurality of under-bump metal layers to be formed on the substrate areas.

Description

technical field [0001] The present invention relates to a semiconductor process, in particular to a semiconductor process with button-shaped bumps. Background technique [0002] The existing conventional semiconductor packaging structure has a substrate, a chip and solder, wherein the conventional semiconductor packaging structure uses solder to electrically bond the bumps of the chip to the connection pads of the substrate. However, due to the increasing volume of current electronic products, The smaller the pitch, the smaller the pitch of the bumps on the chip. In this case, the solder is likely to overflow to the adjacent bumps during reflow and cause a short circuit, which affects the authenticity rate of the product. [0003] It can be seen that the above-mentioned existing semiconductor technology obviously still has inconveniences and defects in structure and use, and needs to be further improved urgently. In order to solve the above-mentioned problems, the relevant ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L23/488
CPCH01L24/11H01L24/14H01L2224/11H01L2224/14051
Inventor 郭志明何荣华林恭安陈昇晖
Owner CHIPBOND TECH