A phase synchronization method, device and FPGA controller of a multi-chip signal converter

Abstract

The embodiment of the invention provides a method and a device for phase synchronization of multiple signal converters and an FPGA (field programmable gate array) controller. The method comprises that an adjustable delay unit receives DCO (digital clock out) signals of any one of the multiple signal converters; a local clock buffer can carry out frequency division on the DCO signals received by the adjustable delay unit, the signals passing through frequency division drive a plurality of associated clock receiving modules to receive DCO signals of the signal converters; the associated clock receiving modules send the received DCO signals to a phase detection logic unit; the phase detection logic unit compares a phase relation of the DCO signals of a master signal converter and a slave signal converter; a signal converter control unit adjusts the phase of the DCO signals of the slave signal converter to be synchronized with that of the DCO signals of the master signal converter according to the phase relation. The method and the device provided by the invention make up a defect that the existing signal converter does not have a phase synchronization design, and reduce the difficulty of circuit debugging.

Description

technical field [0001] The present invention relates to the technical field of signal conversion, and more specifically, relates to a phase synchronization method and device for multi-chip signal converters and an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) controller. Background technique [0002] At present, the signal converter mainly includes DAC (Digital to Analog Converter, digital-to-analog converter), and ADC (Analog to Digital Converter, analog-to-digital converter). With the rapid development of signal processing technology and the development of semiconductor process technology, the performance of signal processing devices has been improved in an all-round way, and high-speed DACs and high-speed ADCs have been widely used in many fields. [0003] figure 1 Shows the internal circuit structure of the high-speed DAC, mainly including: LVDS (LowVoltageDifferentialSignaling, low voltage differential signal) data receiving unit, clock frequency ...

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Problems solved by technology

[0009] In view of this, an embodiment of the present invention provides a phase synchronization method, device, and FPGA controller of a multi-chip signal converter to solve the problem of resetting the phase synchronization of the digital domain clocks of the multi-chip signal converter in the prior art. There are strict timing requirements between the signal and the clock frequency division unit embedded in the signal converter, and the need for the signal converter to provide a reset pin and clock reset function, resulting in difficult implementation problems

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