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Three-dimensional offset-printed memory

A memory and bias technology, applied in the fields of electrical solid state devices, semiconductor devices, semiconductor/solid state device manufacturing, etc., can solve the problems of high cost and limit the wide application of 3D-MPROM

Inactive Publication Date: 2014-03-26
CHENGDU HAICUN IP TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the 22nm node, the cost of a data mask is $250,000, and the cost of a set of x8x2 3D-MPROM data masks (including 16 data masks) is as high as $4 million
Such a high data mask cost will greatly limit the wide application of 3D-MPROM

Method used

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Embodiment Construction

[0036] In order to reduce the number of data masks, the present invention proposes a three-dimensional offset printing memory (3D-oP). It uses offset printing method to enter data. The offset printing method is one of the printing methods. The main printing methods include photo-lithography and imprint-lithography (also known as nano-imprint lithogrpahy, referred to as NIL) (see Chinese patent application "Three-dimensional printing memory"): photolithography The method uses a data mask to input data; while imprinting records uses a data template (template, also known as master, stamp, or mold, etc.) to input data.

[0037] Figure 5A-Figure 5B Represents two printing steps used in an offset printing method. It uses a multi-region data mask8. In this embodiment, the multi-region data mask 8 contains mask patterns for two different storage layers 16A, 16B. They are respectively located in the data mask areas 8a, 8b.

[0038] The offset printing method includes the followi...

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PUM

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Abstract

The invention discloses a three-dimensional offset-printed memory (3D-oP). Compared with a conventional three-dimensional mask programmable read-only memory (3D-MPROM), the three-dimensional offset-printed memory has the characteristic that fewer data mask plates are required, so that the mask plate cost is lower. Mask graphs corresponding to different memory layers / digital bits are combined onto a multi-area data mask plate. In different print steps, offsets of wafers relative to the multi-area data mask plate are different. Therefore, data graphs from the same data mask plate are printed to the data input films with different memory layers / digital bits.

Description

technical field [0001] This invention relates to the field of integrated circuit memories and, more particularly, to mask-programmed read-only memories (mask-ROMs). Background technique [0002] Three-dimensional mask-programmed read-only memory (3D-MPROM) is an ideal medium for mass publishing. US Patent 5,835,396 discloses a 3D-MPROM. Such as figure 1 As shown, 3D-MPROM is a monolithic integrated circuit, which includes a semiconductor substrate 0 and a three-dimensional stack 10 stacked on the substrate. The three-dimensional stack 10 contains M (M≥2) storage layers (such as 10A, 10B) stacked on each other. Each storage layer (such as 10A) contains multiple top address lines (such as 2a), bottom address lines (such as 1a) and storage elements (such as 5aa). Each storage element stores n (n≥1) bits of data. The storage layer (such as 16A, 16B) is coupled with the substrate 0 through contact via holes (such as 1av, 1'av). The substrate circuit 0X in the substrate 0 co...

Claims

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Application Information

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IPC IPC(8): H01L27/112H01L21/8246
Inventor 张国飙
Owner CHENGDU HAICUN IP TECH
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