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means for controlling access to cache structures

A technology for controlling pairing and caching, which is applied in memory systems, instruments, electrical digital data processing, etc., and can solve problems such as expensive caches and poor expansion

Active Publication Date: 2018-08-28
BARCELONA SUPERCOMPUTING CENT CENT NAT DE SUPERCOMPUTACION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, these caches, also known as fully associative caches, are usually expensive in terms of energy and area and do not scale well

Method used

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Embodiment Construction

[0039] In the following description of preferred embodiments, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known elements need not be shown in schematic or block diagram form in order not to obscure the invention.

[0040] It should also be noted that, if not stated otherwise, all functions described herein may be performed in hardware or software or some combination thereof. However, if nothing else is stated, in a preferred embodiment, this function is performed by a processor, such as a computer or an electronic data processor, in accordance with code, eg, computer program code, software and / or integrated circuits, coded to perform the function.

[0041] Execution of a computer program in a computer system, such as a personal computer, involves the ex...

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PUM

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Abstract

The invention relates to a device for controlling the access to a cache structure comprising multiple cache sets during the execution of at least one computer program, the device comprising a module for generating seed values during the execution of the at least one computer program; a parametric hash function module for generating a cache set identifier to access the cache structure, the identifier being generated by combining a seed value generated by the module for generating seed values and predetermined bits of an address to access a main memory associated to the cache structure.

Description

technical field [0001] The invention relates to a method of controlling access to a cache structure comprising a plurality of cache banks when executing at least one computer program. More specifically, the invention relates to a method of guaranteeing that every address accessed by a computer program can be assigned with real probability to any particular cache group of a cache structure. [0002] Furthermore, the invention also relates to an apparatus and a computer program product for controlling access to a cache structure suitable for implementing the method. [0003] The invention can be applied to real-time systems, such as safety-critical real-time systems such as flight control systems. Background technique [0004] A cache is usually a small, block storage buffer that can be used to store information such as code or data, so that programs running on the processing device can execute faster. Typically, a processing device reads from cache faster than from main mem...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0864
CPCG06F12/0864G06F12/1408
Inventor 海梅·阿韦利亚费雷尔爱德华多·基尼奥内斯莫雷诺弗朗西斯科·哈维尔·卡索拉阿尔梅达
Owner BARCELONA SUPERCOMPUTING CENT CENT NAT DE SUPERCOMPUTACION