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Fan-out-type wafer-level packaging structure and manufacturing process

A wafer-level packaging and manufacturing process technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as difficulty, slippage, and dislocation are difficult to control, and achieve the effect of improving warpage

Active Publication Date: 2014-06-25
江苏中科智芯集成科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, it is very difficult to control the warpage of the fan-out packaging using the molding process. The solutions in the prior art are to reduce the warpage from the aspects of material properties and the final shape of the molding; It is also difficult to control the slip and shift caused by (EMC) expansion and contraction

Method used

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  • Fan-out-type wafer-level packaging structure and manufacturing process
  • Fan-out-type wafer-level packaging structure and manufacturing process
  • Fan-out-type wafer-level packaging structure and manufacturing process

Examples

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Embodiment Construction

[0030] The present invention will be further described below in conjunction with specific drawings.

[0031] Such as Figure 9a , Figure 9b As shown: the fan-out wafer level packaging structure includes a chip 100 with a first metal electrode 102a and a second metal electrode 102b and a metal layer 203, and the chip 100 and the metal layer 203 are molded into a whole by a plastic packaging material 501; The front side 100a of the chip 100 is located on the same plane as the front side 501a of the molding material 501, the back side 100b of the chip 100 and a surface 203a of the metal layer 203 are located on the same plane as the back side 501b of the molding material 501, and the height of the metal layer 203 is smaller than that of the chip 100, so that the other surface 203b of the metal layer 203 is located in a different plane from the front 100a of the chip 100; a dielectric layer 901 is arranged on the front 501a of the plastic encapsulation material 501, and a rewiri...

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Abstract

The invention relates to a fan-out-type wafer-level packaging structure and a manufacturing process. The packaging structure is characterized in that when the fan-out-type wafer-level packaging structure is manufactured, the process procedure that the front faces of chips are upward is adopted, a metal layer is manufactured on a carrier wafer firstly, and then through holes are formed according to the arrangement positions of the chips, or the metal layer provided with grooves is directly attached to the carrier wafer in an adhesive mode; the chips are attached to the grooves of the metal layer in an adhesive mode with the front faces of the chips upward, and then the plastic package process is carried out. Accordingly, the fan-out-type wafer-level packaging inner structure is changed, rigidity and the thermal coefficient of expansion of the structure are improved, and warping of the whole wafer and sliding and dislocation, caused by expansion and contraction of plastic package materials, of the wafer can be controlled; additionally, the metal material can play a better role in heat conduction and electromagnet shielding.

Description

technical field [0001] The invention relates to a fan-out wafer-level packaging structure and a manufacturing process, belonging to the technical field of semiconductor packaging. Background technique [0002] Fan-out wafer-level packaging is an embedded package processed at the wafer level, and it is also one of the main advanced packages with a large number of I / Os and good integration flexibility. Fan-out wafer-level packaging technology generally uses individual microchips cut from a wafer and then embedded on a new "artificial" wafer. When embedding, there must be sufficient spacing between microchips for fan-out rerouting. At present, it is very difficult to control the warpage of the fan-out packaging using the molding process. The solutions in the prior art are to reduce the warpage from the aspects of material properties and the final shape of the molding; It is also difficult to control the slippage and shift caused by (EMC) expansion and contraction. Contents ...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L21/98
CPCH01L21/568H01L2224/12105H01L2924/18162H01L2924/3511
Inventor 王宏杰陈南南
Owner 江苏中科智芯集成科技有限公司
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