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Three-dimensional fan-out type PoP packaging structure and manufacturing process

A packaging structure, fan-out technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as difficult warping, slippage, and dislocation that are difficult to control, and achieve improvement warping effect

Active Publication Date: 2014-06-25
江苏中科智芯集成科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, it is very difficult to control the warpage of the PoP solution of the fan-out package using the molding process. The existing solutions are all to reduce the warpage from the aspects of material properties and the final shape of the molding; In addition, the slippage and shift caused by the expansion and contraction of the plastic packaging compound (EMC) are also difficult to control
Therefore, the yield rate of PoP packaging structure production has become a big problem

Method used

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  • Three-dimensional fan-out type PoP packaging structure and manufacturing process
  • Three-dimensional fan-out type PoP packaging structure and manufacturing process
  • Three-dimensional fan-out type PoP packaging structure and manufacturing process

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Embodiment Construction

[0054] The present invention will be further described below in conjunction with specific drawings.

[0055] As shown in Figure 223a, Figure 22b As shown: the three-dimensional fan-out PoP packaging structure includes upper and lower layers of fan-out packaging units; Figure 21a , Figure 21b As shown, the fan-out packaging unit includes a first fan-out wafer level package 10, a second fan-out wafer level package 20 stacked on the front of the first fan-out wafer level package 10 and The backside rewiring layer 50 disposed on the backside of the first fan-out wafer level package 10 (the front side of the first fanout wafer level package 10 can be stacked in turn with one layer, two layers, three layers or four layers etc. layer second fan-out wafer level package body 20, Figure 21a , Figure 21b Only one stack is shown);

[0056] Such as Figure 21a , Figure 21b As shown, the first fan-out wafer level package 10 includes a first chip 101 with metal electrodes 1011, ...

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Abstract

The invention relates to a three-dimensional fan-out type PoP packaging structure and a manufacturing process. Metal layers are manufactured on a carrying sheet through the process with the front faces of chips facing upwards, grooving is conducted according to the arrangement positions of the chips, and electrodes connected with other packaging units are manufactured according to the requirements. Rerouting layers are manufactured on the front faces of the chips after plastic package, and bonding pads of the chips are fanned out to form first layer chip circuits. Second layer chips are manufactured by repeating the process with the front faces of the chips facing upwards, and the corresponding chip and the corresponding metal layer are pasted on the first packaging unit so that the first packaging unit can be connected with the previous packaging unit. Plastic package, drilling and metal filling are then conducted, and RDL manufacturing is conducted on the second layer chips. Multiple layers of chips are stacked by repeating the stacking process, or lower bump metal layer manufacturing and ball planting are conducted on RDL layers. The carrying sheet is removed after ball planting is completed, a back face rerouting layer is arranged on the back face of each first layer chip, the corresponding packaging unit is obtained, and the packaging units are stacked to form the PoP packaging structure. According to the three-dimensional fan-out type PoP packaging structure and the manufacturing process, slip dislocation caused by warping and expansion and contraction of plastic package materials can be effectively reduced.

Description

technical field [0001] The invention relates to a three-dimensional fan-out PoP packaging structure and a manufacturing process, belonging to the technical field of semiconductor packaging. Background technique [0002] As the main way of packaging high-density integration at present, PoP (package on package, package on package) has received more and more attention. Chip stacking is the main way to increase the density of electronic packaging, and PoP design has been widely developed and applied in the industry. At present, it is very difficult to control the warpage of the PoP solution of the fan-out package using the molding process. The existing solutions are all to reduce the warpage from the aspects of material properties and the final shape of the molding; In addition, the slippage and shift caused by the expansion and contraction of the plastic encapsulant (EMC) are also difficult to control. Therefore, the yield rate of PoP packaging structure production becomes a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/065H01L23/31H01L21/98
CPCH01L2224/04105H01L2224/12105H01L2224/32145H01L2224/32225H01L2224/73267H01L2224/92244H01L2225/1035H01L2225/1058H01L2924/18162H01L25/105H01L2224/94H01L2224/19H01L2224/03H01L2924/00012
Inventor 王宏杰陈南南
Owner 江苏中科智芯集成科技有限公司
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