14results about How to "Improve warpage" patented technology

The invention discloses a processing method for improving picosecond cutting board warping of an FPCOIL product, which comprises the following steps that a circuit board containing the product and a laser carrier capable of containing the circuit board are provided, and the laser carrier comprises a lower jig and an upper jig; the lower jig is placed on a working table; the circuit board is placed in the lower jig, and then the upper jig is placed at the upper end of the lower jig; the working table board adsorbs a circuit board through a lower jig, and a plurality of exhaust holes are formed in the lower jig; and cutting the circuit board by using a picosecond laser. The structure that the lower jig and the upper jig are fixed in a magnetic attraction mode is adopted for improving warping of a product board, the lower jig is placed on the working table, the whole circuit board is placed in the lower jig, a plurality of exhaust holes distributed in the periphery of the product are formed in the lower jig, effective attraction of the working table to the circuit board is facilitated, and the follow-up laser cutting precision is improved; and the upper jig is pressed on the edge area of the circuit board, so that the warping of the product can be improved.

The utility model belongs to the field of additive manufacturing, and relates to a powder spreading device which comprises a supporting seat, a powder spreading roller assembly, a vibration generating mechanism and a driving device. The driving device is arranged on the supporting seat and is connected with the powder spreading roller group; the driving device drives the powder spreading roller assembly to work; and the vibration generating mechanism is arranged on the powder spreading roller assembly. The utility model provides the powder spreading device capable of effectively improving the powder spreading density.

This invention discloses a novel POP (Position-on-Pack) packaging structure that improves heat dissipation and reduces warpage. The structure includes: a multilayer substrate, comprising at least a bottom substrate and a top substrate; a chip; a ceramic structural layer embedded within the bottom substrate, wherein the ceramic structural layer has through-holes that allow electrical conductivity between the upper and lower layers; and an indium wafer structural layer, the lower surface of which is mounted to the upper surface of the chip, and the upper surface of which is soldered to the lower surface of the top substrate. This invention improves warpage issues caused by thermal stress during packaging by adding a ceramic structural layer inside the bottom substrate. The through-holes in the ceramic structural layer create electrical conductivity between the upper and lower layers, ensuring that the ceramic structural layer does not affect the conductivity of the bottom substrate. Furthermore, by mounting an indium wafer on the upper surface of the chip in the bottom packaging structure and adding a soldering surface to the lower surface of the top substrate for soldering to the indium wafer, the overall POP packaging achieves heat dissipation through the indium wafer's connection to the external environment.

This application relates to a photovoltaic module and an electrical device. The photovoltaic module includes a backsheet layer, which comprises a substrate layer and an inorganic ceramic coating located on at least one side of the substrate layer. This application reduces the overall shrinkage variation of the backsheet layer by forming an inorganic ceramic coating on the surface of the substrate layer. This inorganic ceramic coating constrains the expansion or contraction of the substrate layer, thereby improving the warpage problem of the backsheet layer.

The present disclosure provides a carrier assembly for carrying semiconductor package strips, comprising: a carrier body comprising a housing, the housing comprising side walls with support slots for carrying the semiconductor package strips inside the housing respectively, and the housing defining a front opening and a rear opening between the side walls to allow placement and displacement of the semiconductor package strips; and a pair of clamping devices for applying a clamping force to the semiconductor package strips against the support slots respectively, and each of the pair of clamping devices comprising: a locking plate; a strip contact extension extending from the locking plate and insertable through one of the front opening and the rear opening of the housing; and a locking member for moving the strip contact extension between a locked position and an unlocked position, wherein in the locked position, a semiconductor package strip is pressed by the respective strip contact extension against the support slot.

This disclosure provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes: providing a first wafer; the first wafer having a first side and a second side opposite to each other in a first direction; bonding the first wafer to a carrier wafer via the first side; thinning the second side of the first wafer; forming a rigid thermally conductive film covering the second side of the first wafer; removing the carrier wafer; dicing the first wafer and the rigid thermally conductive film along the first direction to divide the first wafer into a plurality of chips; the rigid thermally conductive film covering the second side of the plurality of chips; bonding the first side of the plurality of chips to a second wafer; and bonding a third wafer to the rigid thermally conductive film.

The present disclosure provides a carrier device for supporting a silicon wafer in a horizontal direction so that a first surface of the silicon wafer is polished from above, the carrier device comprising: a housing; a soft portion at least partially surrounded by the housing, the soft portion being arranged to be in contact with a second surface of the silicon wafer through an upper surface thereof so as to deform according to a shape of the second surface when the silicon wafer is polished, wherein the first surface is opposite to the second surface. The carrier device can provide uniform support for different silicon wafers during polishing, effectively avoid damage caused by stress concentration, and make the polishing amount of different areas of the silicon wafer meet the expectation, thereby obtaining a silicon wafer with reduced bending and warping and improved surface quality.

The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil substrate processing equipment. The application discloses a vertical warping improvement device for copper foil substrates and relates to the technical field of copper foil The application discloses a vertical warping improvement device for copper foil substrates and relates to the

The invention provides a chip support plate and a manufacturing method thereof, and a chip packaging structure, the chip support plate comprises a substrate and a plurality of rewiring layers, the substrate comprises a first surface and a second surface which are oppositely arranged, the substrate is provided with a plurality of conductive holes, the conductive holes are recessed from the first surface to the second surface, and the conductive holes are filled with conductive structures; the multiple redistribution layers are located on the first surface of the substrate, at least part of the redistribution layers are electrically connected with the conductive structures, the redistribution layers comprise dielectric layers, and the materials of the dielectric layers and the substrate both comprise inorganic materials. The substrate and the dielectric layer of the rewiring layer are both made of inorganic materials, so that the substrate and the dielectric layer have the characteristics of low dielectric constant and low loss, meanwhile, the design can also enable the thermal expansion coefficients of the whole carrier plate to be similar, and the buckling deformation of the carrier plate in the manufacturing process is greatly improved.

The invention provides a display panel, a preparation method thereof and a display device. The problem that in the prior art, the yield of display products is low is solved. The display panel comprises a substrate, a conductive layer, a flat layer, a first electrode layer and an isolation structure, wherein the conductive layer is located on one side of the substrate; the flat layer is located on one side of the conductive layer away from the substrate; a via hole is formed in the flat layer; the first electrode layer is located on the side, away from the substrate, of the flat layer and electrically connected with the conductive layer through a via hole; the isolation structure is located on one side of the first electrode layer away from the substrate; the isolation structure comprises a first part and a second part, the first part is located on the side, close to the substrate, of the second part, and the orthographic projection of the first part on the substrate is located in the orthographic projection of the second part on the substrate; the second part comprises at least one stress release area, and the orthographic projection of the stress release area on the substrate is located in the orthographic projection of the via hole on the substrate.

The application provides a packaging carrier and a machine, which comprises a carrier plate, a pressing plate and a plurality of lifting pads; the carrier plate is used for carrying a substrate, the upper surface of the carrier plate is provided with a first groove, and the first groove is used for providing a deformation space for the substrate; the pressing plate is located on the upper surface of the substrate and exposes the upper surface of the part of the substrate which is in contact with a chip, and is used for providing a downward pressure to the substrate; the plurality of lifting pads are arranged in an array in the first groove, the lifting pads are movable in the vertical direction, the upper surface of the lifting pads is lower than the upper surface of the carrier plate when the lifting pads are moved to a lower limit position, and the upper surface of the lifting pads is higher than the upper surface of the carrier plate when the lifting pads are moved to an upper limit position. The packaging carrier of the application has a wide range of applications, and the warping conditions of the substrate and the chip can be made consistent by adjusting the height of the lifting pads, the adjustment is flexible, the packaging carrier is not customized, the work efficiency is greatly improved, and the production cost is reduced.

This invention provides a bonding wafer and its fabrication method. The bonding wafer fabrication method includes: providing a support substrate, wherein a first oxide layer and a second oxide layer are respectively formed on two opposing surfaces of the support substrate; forming a protective layer on the surface of the first oxide layer, the protective layer covering the first oxide layer; providing a device substrate, wherein a buried oxide layer is formed on the surface of the device substrate; bonding the support substrate and the device substrate, with the second oxide layer facing the buried oxide layer; performing a lift-off process to remove a portion of the device substrate, such that the remaining device substrate, support substrate, first oxide layer, and second oxide layer constitute the bonding wafer; and performing a cleaning process and a heat treatment process on the bonding wafer using the protective layer as a mask. Because the surface of the first oxide layer is covered by the protective layer, the first oxide layer is protected, thereby preventing a reduction in the thickness of the first oxide layer and avoiding any impact on the warpage of the bonding wafer due to a reduction in the thickness of the first oxide layer.

This utility model relates to the field of printed circuit board manufacturing technology and discloses an anti-warping rigid lamination board. Both the first and second core boards are used to carry signal lines, and both the first and second adhesive layers are used to separate the signal lines and bond the anti-warping rigid lamination board. The first and second stacks, made of different materials, are bonded together. The thermal shrinkage of the first stack is greater than that of the second stack. To address the mixed lamination of the first and second stacks, a buffer layer is bonded to the side of the second stack away from the first stack to adjust the shrinkage balance between the first and second stacks. This ensures that the anti-warping rigid lamination board achieves symmetrical thermal shrinkage force balance after lamination, thus improving the warping problem. The structure is simple and facilitates control of warping deformation caused by mixed lamination of different materials, ensuring that the degree of warping meets the conventional control process requirements of printed circuit boards.