Wafer-level fan-out PoP encapsulation structure and making method thereof

Abstract

The invention discloses a wafer-level fan-out PoP encapsulation structure and a making method thereof. The wafer-level fan-out PoP encapsulation structure is formed by stacking at least one fan-out PoP encapsulation units, each two adjacent fan-out PoP encapsulation units are connected through a second welding ball and coated and sealed by adopting a second plastic sealing material, each fan-out PoP encapsulation unit comprises an IC chip, a first plastic sealing material, a second binding material, a metal salient point structure, a first metal layer, a second metal layer, a first rewiring metal routing layer, a first dielectric material layer, a second rewiring metal routing layer, a second dielectric material layer, a first welding ball and the second welding ball, a bonding pad of each IC chip is connected with the corresponding first rewiring metal routing layer, each metal salient point structure forms a molded plastic through hole, and three-dimensional integrated interconnection between an upper encapsulating body as well as a lower encapsulating body in each fan-out PoP encapsulation unit and an external structure is realized through the corresponding molded plastic through hole. The making method mainly includes arranging a metal substrate wafer on a first carrier wafer; making the metal salient point structure on the surface of the metal substrate wafer; feeding the chip; plastically sealing, making the first rewiring metal routing layer; arranging a second carrier wafer, removing the first carrier wafer, etching the lower surface of the metal substrate wafer to form the second rewiring metal routing layer; performing stacking and reflow soldering; removing the second carrier wafer; forming the fan-out PoP encapsulation unit after ball placing and reflow soldering processes; performing stacking and reflow soldering on the fan-out PoP encapsulation units; and forming the wafer-level fan-out PoP encapsulation structure after plastic sealing. By the wafer-level fan-out PoP encapsulation structure and the making method, the problems of encapsulating density, cost and reliability of existing PoP encapsulation technology are solved.

Description

technical field [0001] The invention relates to the field of microelectronic packaging technology and three-dimensional integration technology, in particular to a three-dimensional wafer-level fan-out PoP packaging technology and a manufacturing method thereof. Background technique [0002] With the continuous development of electronic packaging products in the direction of high density, multi-function, low power consumption, and miniaturization, the system-in-package (SiP) using three-dimensional integration technology has achieved rapid development. The Through Silicon Via (TSV) technology solution is the optimal solution for realizing 3D integration technology due to its characteristics of the highest stacking density, the smallest size, greatly improved chip speed and reduced power consumption. However, the current TSV technology faces serious problems such as manufacturing difficulty, process cost, yield rate and reliability of finished products. The existing mature th...

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Problems solved by technology

[0004] The present invention proposes a packaging structure and manufacturing method for the three-dimensional PoP packaging technology to solve the problems of packaging density, cost and reliability existing in the existing PoP packaging technology

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