A misalignment detection and error correction circuit in serdes technology

Abstract

The invention belongs to the technical field of SerDes serial communication and particularly relates to a malposition detection and error correction circuit in the SerDes technology. The malposition detection and error correction circuit in the SerDes technology is composed of a sending end digital circuit and a receiving end digital circuit. At the sending end, a check code generation circuit is started by a sending end controller to sequentially generate an N-digit full-1 synchronizing signal and a check signal with only the most significant digit being 0, and the N-digit full-1 synchronizing signal and the check signal are gated and sent to a Serializer module through an either-or MUX and then are transmitted to the receiving end digital circuit after passing through a difference transmission channel and a Deserializer; at the receiving end, a malposition detection circuit detects and judges whether malposition occurs on received data; the correct data bit order is obtained through recovery and correction by means of an error correction circuit module according to the bit number, actually appearing, of 0 in a received check node, and finally the correct data bit order is output. The malposition detection and error correction circuit in the SerDes technology is obtained through a digital circuit and has the advantages that programmability is achieved, the logic is simple, and the flexibility is good. The malposition detection and error correction circuit in the SerDes technology is compatible with the design flow of a digital integrated circuit design which is commonly used at present and based on the hardware description language.

Description

technical field [0001] The invention belongs to the technical field of SerDes serial communication, in particular to a dislocation detection and error correction circuit in the SerDes technology. Background technique [0002] With the development of electronic communication technology, the industry puts forward higher and higher requirements for the transmission rate and channel bandwidth of the data interface. Traditional parallel interfaces, such as IEEE 1284, PATA, etc., cannot meet the increasingly miniaturized requirements of the system because of the large resource consumption of the channel bit width. Therefore, serial interfaces with faster speed and smaller bit width are gradually becoming the mainstream solution. [0003] SerDes interface technology is the abbreviation of English Serializer (serializer) / Deserializer (deserializer). It is a widely used time division multiplexing (Time Division Multiplex, TDM) and point-to-point (Point-to-Point, P2P) serial communi...

AI Technical Summary

Problems solved by technology

During data transmission, due to the uncertainty of the channel delay, the SerDes receiving end cannot accurately identify the position of the highest bit in the serial signal, resulting in misalignment of the output parallel data. The schematic diagram of the process is shown in figure 1 shown

If the traditional analog circuit is used to solve the problem of receiving data misalignment, it will bring about a great increase in design complexity and inconvenience in debugging and verification.

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