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Preparation method of multi-bit highly integrated vertical structure memory

A vertical structure, highly integrated technology, applied in the field of micro-nano, can solve time-consuming, cost-consuming and other problems

Inactive Publication Date: 2016-09-14
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Compared with other processes, the etching and CMP process optimization for new materials is a relatively time-consuming and expensive process, which is also the biggest bottleneck to be faced in the verification of new storage materials

Method used

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  • Preparation method of multi-bit highly integrated vertical structure memory
  • Preparation method of multi-bit highly integrated vertical structure memory
  • Preparation method of multi-bit highly integrated vertical structure memory

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Embodiment Construction

[0019] see figure 1 , figure 2 and image 3 As shown, the present invention provides a method for preparing a multi-bit highly integrated vertical structure memory, the method comprising:

[0020] 1) On the substrate 101, a first electrothermal isolation material layer 102A is deposited, and a mask layer is spin-coated on the first electrothermal isolation material layer 102A, and a first mask groove is formed by photolithography;

[0021] The material of the substrate 101 can be silicon, gallium nitride, sapphire, silicon carbide, gallium arsenide or glass; the function is to provide planarization support necessary for device fabrication.

[0022] 2) Depositing a first electrode material layer on the first mask opening and the exposed upper surface of the first electrothermal isolation material layer 102A;

[0023] 3) Etching and removing the grooves in the first mask, and peeling off to form the first lower electrode 104A;

[0024] 4) Depositing the second electrotherma...

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Abstract

A method for preparing a multi-bit high-integration vertical structure memory, comprising: depositing a first electrothermal isolation material layer on a substrate; depositing a first electrode material layer, depositing a second electrothermal isolation material layer; depositing a second electrothermal isolation material layer; electrode material layer, forming the second lower electrode; depositing the third electrothermal isolation material layer; making the third lower electrode; depositing the fourth electrothermal isolation material layer; depositing the storage material layer and the fourth electrode material layer in sequence, depositing the first Five layers of electrothermal isolation material; deposit the fifth electrode material layer; open holes in the fifth electrothermal isolation material layer to the upper surface of the upper electrode; deposit the sixth electrode material layer, and remove the sixth mask to open grooves and peel off to form three Second test electrode. The invention is compatible with the existing CMOS process for quickly realizing small unit power consumption and large unit area integration, and has very good industrial application prospects.

Description

technical field [0001] The invention relates to the field of micro-nano technology, in particular to a method for preparing a multi-bit highly integrated vertical structure memory. Background technique [0002] The accelerated development of high-tech industries and basic service facilities has higher and higher requirements for fast computing and efficient storage, and the improvement of CPU processing capabilities is increasingly dependent on the speed and power consumption of memory chips. Therefore, how to develop efficient storage It will become one of the key technologies that urgently need a breakthrough in the future. Phase change memory PCRAM (phase change random access memory) is non-volatile. Compared with most current memories, it has the advantages of small device size, low power consumption, fast reading speed, radiation resistance, multi-level storage and compatibility with Compatibility with existing CMOS processes and many other advantages. With a similar ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L45/00
Inventor 付英春王晓峰杨富华
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI