Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of semiconductor chip cracks, cracks, accumulated shocks, etc.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 Embodiment approach
[0021] figure 1 It is a figure which shows the structure of the semiconductor device of 1st Embodiment. Such as figure 1 The illustrated semiconductor device 1 includes a wiring board 2 as a circuit base material. For the wiring substrate 2 , for example, a wiring mesh (not shown) is provided on the surface and / or inside of an insulating resin substrate and / or a ceramic substrate, specifically a printed circuit board using an insulating resin such as glass-epoxy resin. As the circuit base material, instead of the wiring board 2, a silicon package and / or a lead frame may be used. The wiring board 2 has a first surface 2a serving as a surface on which external terminals are formed, and a second surface 2b serving as a mounting surface for a semiconductor chip. although figure 1 The illustration is omitted, but on the first surface 2a of the wiring substrate 2, external terminals for BGA packaging (protruding terminals based on solder balls, etc.) and / or external terminals fo...
no. 2 Embodiment approach
[0039] Second, refer to Figure 4 and Figure 5 The structure of the semiconductor device 21 of the second embodiment will be described. In addition, the same code|symbol is attached|subjected to the same part as 1st Embodiment, and the description of a part is abbreviate|omitted. In the semiconductor device 21 of the second embodiment, as in the first embodiment, the electrical connection between the electrode pads 11 of the semiconductor chips 9A to 9D to be relay-bonded and the connection pads 3B of the wiring board 2 is performed via the semiconductor chip 9A except the lowermost layer. The electrode pad 11 of any one of the semiconductor chips 9B to 9D is implemented. However, in the second embodiment, electrode pads 11 of the semiconductor chips (9B, 9C) between the lowermost semiconductor chip 9A and the uppermost semiconductor chip 9D are used for electrical connection to the connection pads 3B of the wiring board 2 .
[0040] Figure 4 and Figure 5 A state in wh...
no. 3 Embodiment approach
[0051] Second, refer to Image 6 and Figure 7 The structure of the semiconductor device 31 of the third embodiment will be described. In addition, the same code|symbol is attached|subjected to the same part as 1st Embodiment, and the description of a part is abbreviate|omitted. The semiconductor device 31 of the third embodiment has a structure in which relay bonding is performed from the electrode pads 11 of the semiconductor chip 9B on the second layer to the electrode pads 11 of the semiconductor chip 9D on the fourth layer, and the semiconductor chip 9A on the lowermost layer The electrode pads 11 and the electrode pads 11 of the relay-bonded semiconductor chips 9B to 9D are electrically connected to the connection pads 3B of the wiring board 2 , respectively. Furthermore, similarly to the second embodiment, semiconductor chips 9A to 9D including the structure of the wiring board 2 and / or the first chip group 5 of the semiconductor device 31 of the third embodiment, and...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More - R&D
- Intellectual Property
- Life Sciences
- Materials
- Tech Scout
- Unparalleled Data Quality
- Higher Quality Content
- 60% Fewer Hallucinations
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com



