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Semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of semiconductor chip cracks, cracks, accumulated shocks, etc.

Active Publication Date: 2017-04-19
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If this continuous implementation of three bonding steps from the semiconductor chip group on the lower side to the overhanging semiconductor chip on the lowermost layer, to the stitch connection on the bump, and then to the ball connection on the stitch, not only the accumulated bonding impact during bonding, since the protruding part may be bent during bonding, cracks and / or cracks are likely to occur on the semiconductor chip at the bottom layer, etc.

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0021] figure 1 It is a figure which shows the structure of the semiconductor device of 1st Embodiment. Such as figure 1 The illustrated semiconductor device 1 includes a wiring board 2 as a circuit base material. For the wiring substrate 2 , for example, a wiring mesh (not shown) is provided on the surface and / or inside of an insulating resin substrate and / or a ceramic substrate, specifically a printed circuit board using an insulating resin such as glass-epoxy resin. As the circuit base material, instead of the wiring board 2, a silicon package and / or a lead frame may be used. The wiring board 2 has a first surface 2a serving as a surface on which external terminals are formed, and a second surface 2b serving as a mounting surface for a semiconductor chip. although figure 1 The illustration is omitted, but on the first surface 2a of the wiring substrate 2, external terminals for BGA packaging (protruding terminals based on solder balls, etc.) and / or external terminals fo...

no. 2 Embodiment approach

[0039] Second, refer to Figure 4 and Figure 5 The structure of the semiconductor device 21 of the second embodiment will be described. In addition, the same code|symbol is attached|subjected to the same part as 1st Embodiment, and the description of a part is abbreviate|omitted. In the semiconductor device 21 of the second embodiment, as in the first embodiment, the electrical connection between the electrode pads 11 of the semiconductor chips 9A to 9D to be relay-bonded and the connection pads 3B of the wiring board 2 is performed via the semiconductor chip 9A except the lowermost layer. The electrode pad 11 of any one of the semiconductor chips 9B to 9D is implemented. However, in the second embodiment, electrode pads 11 of the semiconductor chips (9B, 9C) between the lowermost semiconductor chip 9A and the uppermost semiconductor chip 9D are used for electrical connection to the connection pads 3B of the wiring board 2 .

[0040] Figure 4 and Figure 5 A state in wh...

no. 3 Embodiment approach

[0051] Second, refer to Image 6 and Figure 7 The structure of the semiconductor device 31 of the third embodiment will be described. In addition, the same code|symbol is attached|subjected to the same part as 1st Embodiment, and the description of a part is abbreviate|omitted. The semiconductor device 31 of the third embodiment has a structure in which relay bonding is performed from the electrode pads 11 of the semiconductor chip 9B on the second layer to the electrode pads 11 of the semiconductor chip 9D on the fourth layer, and the semiconductor chip 9A on the lowermost layer The electrode pads 11 and the electrode pads 11 of the relay-bonded semiconductor chips 9B to 9D are electrically connected to the connection pads 3B of the wiring board 2 , respectively. Furthermore, similarly to the second embodiment, semiconductor chips 9A to 9D including the structure of the wiring board 2 and / or the first chip group 5 of the semiconductor device 31 of the third embodiment, and...

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PUM

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Abstract

To provide a semiconductor device that suppresses the occurrence of cracks and / or cracks during wire bonding of a semiconductor chip in an extended state. The semiconductor device 1 of the embodiment includes: a first chip group 5 including a first semiconductor chip 4 mounted on a circuit base material 2; a second chip group 10 including a plurality of second semiconductor chips stacked on the first chip group 5; chip9. The second semiconductor chips 9 are stacked in steps such that the lowermost second semiconductor chip 9A protrudes from the first chip group 5 . The wiring board 2 and the second semiconductor chip 9 are electrically connected by the second metal lead 13 . The second metal lead 13 is connected to the second electrode pad 11 of the lowermost second semiconductor chip 9A by only one ball bonding.

Description

[0001] Related Patent Applications [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2013-61231 (filing date: March 25, 2013). This application includes the entire contents of the basic application by referring to this basic application. technical field [0003] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same. Background technique [0004] In order to achieve miniaturization and higher functionality of semiconductor devices, stacked semiconductor devices in which a plurality of semiconductor chips are stacked and sealed in one package have been put into practical use. For example, in order to increase the capacity of a semiconductor memory, memory chips are stacked in multiple stages on a wiring board. When wire bonding is applied to electrically connect the wiring board and the memory chip, a structure in which a plurality of memory chips are stacked ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L23/488H01L21/60
CPCH01L24/48H01L2224/32145H01L2224/32225H01L2224/48145H01L2224/48465H01L2224/48479H01L2224/49429H01L2224/73265H01L2225/06562H01L2224/45144H01L2224/83191H01L2924/00014H01L2924/15787H01L2924/181H01L2224/45H01L2224/48H01L2224/49H01L2224/45015H01L2924/00H01L2924/00012H01L2224/4554
Inventor 渡边昭吾
Owner KIOXIA CORP
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