Method for detecting potential of node inside chip
A technology for internal nodes and detection chips, which is applied in the direction of circuit, electrical components, semiconductor/solid-state device testing/measurement, etc., can solve problems such as meaningless measurement and short circuit, and achieve the effect of improving the level of failure analysis
Inactive Publication Date: 2015-01-28
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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In the figure, the measurement node A located at 6AL, the measurement node B located at 5AL, and the measurement node C located at 4AL can monitor the signal through the FIB growth pad, but the measurement nodes D, E and F, Since its top is covered by the upper metal interconnection layers 4AL, 5AL, and 6AL, if the FIB is etched downward to touch the measurement nodes D, E, and F, it must penetrate the upper metal, so a short circuit has occurred, and the measurement becomes useless. significance
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[0023] The method for detecting the internal node potential of the chip according to the present invention comprises the following steps:
[0024] The first step is to select a sample chip. The sample chip is a packaged chip. If it is a bare chip, it needs to be packaged before proceeding to the subsequent steps. Such as figure 2 and image 3 As shown, there is no requirement for the form of the package, and various packages are available. Grind the back of the sample chip to the target layer, rough grind away 5-200 μm and keep 2-20 μm according to the thickness of the sample chip.
[0025] In the second step, the back surface of the sample chip is continuously etched by chemical etching until the insulating isolation layer is exposed; Figure 4 shown (for convenience of illustration, with figure 2 , image 3 different, Figure 4 Turn the sample chip 180 degrees to make the back side of the sample chip face up, and the same Figure 5 , 6 Also flipped), some of the in...
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Abstract
The invention discloses a method for detecting the potential of a node inside a chip, comprising the following steps: selecting a sample chip and grinding the back of the sample chip to a target level; corroding the back of the sample chip by a chemical corrosion method until an insulation and isolation layer is exposed; passing through the insulation layer with a focused ion beam machine to etch out a connection pathway, filling the connection pathway with platinum metal, and forming a pad at the tail end of the connection pathway; transferring the sample chip to a manual testing machine, carrying out pre-needling on the pad with a probe having a ground potential, and releasing charges; and applying a corresponding test signal to the probe, testing the sample chip and detecting the change of a pad node signal. By adopting the method, potential detection can be carried out on multi-level metal interconnection from both the front and the back, and the level of chip failure analysis is improved.
Description
technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method for detecting the internal node potential of a chip in integrated circuit failure analysis. Background technique [0002] With the continuous development of integrated circuit technology, the size of the chip is continuously reduced and the performance is continuously improved, and the number of layers of the chip is also increasing. When the product is in the R&D or manufacturing stage, if there is an abnormality, it becomes very important to measure the internal node potential to distinguish which part of the circuit is abnormal. If the measurement node is on the top layer of the chip or close to the top layer, it is relatively simple to make the connection point of the FIB (focused ion beam) circuit; Very prone to short circuits, FIB becomes very difficult. [0003] Such as figure 1 Shown is a cross-sectional view of the metal interconnection layer of a sam...
Claims
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Login to View More IPC IPC(8): H01L21/66
CPCH01L22/14H01L22/32
Inventor 马香柏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP