Array substrate, manufacturing method thereof, and display device
A technology of array substrates and substrate substrates, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve the problems of high power consumption of display devices, large power consumption of gate drive circuits, complex timing of gate drive signals, etc. problem, to achieve the effect of simple timing, low power consumption and sufficient charging
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Embodiment 1
[0073] An embodiment of the present invention provides an array substrate, such as figure 1 and figure 2 As shown, the array substrate includes a base substrate 1, gate lines 2 and pixels located on the base substrate 1, each pixel includes a first thin film transistor 3 and a pixel electrode 4, the nth gate line 2 controls the nth row A thin film transistor 3 charges the pixel electrode 4 in the nth row, each pixel also includes a second thin film transistor 5, and the n-1th gate line 2 controls the second thin film transistor 5 in the nth row to charge the pixel electrode 4 in the nth row Precharge, wherein, n is a positive integer greater than or equal to 2. It should be noted that the maximum value of n is the number of gate lines 2 on the array substrate.
[0074] It should be noted that, the first thin film transistors in the nth row and the pixel electrodes in the nth row both refer to the first thin film transistors and pixel electrodes controlled by the nth gate li...
Embodiment 2
[0092] An embodiment of the present invention provides a method for manufacturing the array substrate described in Embodiment 1, which can form Figure 1-4 As shown in the structure, the manufacturing method includes as Figure 5 The steps shown are as follows:
[0093] Step S501, forming a pattern including gate lines.
[0094] Step S502, forming a first thin film transistor and a second thin film transistor.
[0095] Step S503, forming a pixel electrode to form a pixel including a first thin film transistor, a second thin film transistor and a pixel electrode.
[0096] Among them, the nth gate line 2 controls the first thin film transistor 3 of the nth row to charge the nth row of pixel electrodes 4, and the n-1th gate line 2 controls the nth row of the nth second thin film transistor 5 to charge the nth row of pixel electrodes 4. Perform precharging, where n is a positive integer greater than or equal to 2. It should be noted that the maximum value of n is the number of...
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