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System and method for realizing PID remapping of mpeg TS stream

An implementation method and system implementation technology, which is applied in the field of MPEGTS stream PID remapping implementation system, can solve the problems of increasing system delay, timing and resource waste, and achieve the elimination of resource waste, reduction of delay, and saving of memory resources The effect of spending

Active Publication Date: 2017-12-12
成都德芯数字科技股份有限公司
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Problems solved by technology

[0003] Taking the processing of 2048 PIDs as an example, it is necessary to open up additional storage space to store each TS packet, so that the 2048 PIDs in RAM can be queried. Taking Altera's FPGA Cyclone IV EP4CE40 as an example, it needs to consume 2 more M9K memories resources, and increase the delay of the system, which brings waste of timing and resources to the design

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  • System and method for realizing PID remapping of mpeg TS stream
  • System and method for realizing PID remapping of mpeg TS stream
  • System and method for realizing PID remapping of mpeg TS stream

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[0024] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0025] Any feature disclosed in this specification (including any appended claims, abstract and drawings), unless expressly stated otherwise, may be replaced by alternative features which are equivalent or serve a similar purpose. That is, unless expressly stated otherwise, each feature is one example only of a series of equivalent or similar features.

[0026] A system for implementing PID remapping of MPEG TS streams, including a PID extraction module that parses the TS stream and extracts the PID in the TS stream as old PID; a mapping table generation module that replaces the extracted old PID w...

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Abstract

The invention provides an MPEG TS stream PID remapping achievement system and method. The MPEG TS stream PID remapping achievement method comprises the steps of analyzing a TS stream and extracting a PID in the TS stream as an old PID; using the extracted old PID and a new PID replaced in the mapping process to form a PID mapping table; sorting the PID mapping table according to an old PID value and the sequence from small to large and storing the PID mapping table; extracting the PID in a TS stream package and querying the PID mapping table in a storage module when the TS stream package is input; comparing the PID value extracted in the TS stream with the old PID value in a certain address of the queried PID mapping table, exiting query if the values are equal, using the new PID to replace the extracted PID, deterring upward or downward query according to a comparison result and the address of the mapping table and continuing to perform query and comparison if the values are different. Compared with a traditional query mode, resource waste is eliminated, a large amount of memorizer resource expenditure is saved, and system delay is reduced.

Description

technical field [0001] The invention relates to a system and method for realizing remapping of MPEG TS stream PID, in particular to a system and method for realizing remapping of MPEG TS stream PID in DVB system. Background technique [0002] At present, the general PID remapping method stores the mapping relationship of PID input and output in a RAM inside the FPGA. When a TS flow packet is input to FPGA, FPGA starts to extract the PID in the packet, and queries the output PID corresponding to the input PID in the RAM with the PID mapping relationship. In MPEG2, the packet length of each TS stream is 188, so when the number of PIDs to be processed exceeds 188, each TS packet needs to be registered to increase the time required for the query. [0003] Taking the processing of 2048 PIDs as an example, it is necessary to open up extra storage space to store each TS packet, so that the 2048 PIDs in RAM can be queried. Taking Altera's FPGA Cyclone IV EP4CE40 as an example, it n...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/10G06F17/30G06F12/02
Inventor 李俊牛伟
Owner 成都德芯数字科技股份有限公司
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