a tuning method
A technology of trimming and setting methods, which is applied in the direction of measuring devices, instruments, measuring electronics, etc., can solve problems such as inconsistencies in chip trimming values, and achieve the effect of shortening the test time
Active Publication Date: 2017-08-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
In order to achieve this goal, some chips require negative trimming for this feature, while others require positive trimming, resulting in inconsistencies in the trimming values of each chip.
[0003] However, when large-scale logic testing instruments test chips, from the perspective of production, they often use large-scale simultaneous testing, which is in contradiction with the purpose of the above-mentioned adjustment. In order to balance the two, it is necessary to find a more effective method. Improve the accuracy of trimming while ensuring mass production
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Embodiment Construction
[0027] The adjustment method of the present invention, its step can be as follows:
[0028] Through technical judgment, it can be analyzed whether the test unit to be detected belongs to the middle area of the wafer or the peripheral area, so that the trimming target value of the middle area and the trimming target value of the peripheral area can be separated;
[0029] Wherein, the method for setting the trimming target value for the middle region of the wafer can be as follows:
[0030] 1) Before starting the test of each wafer, select more than 2 positions in the middle area of the wafer that can represent the distribution characteristics of the wafer surface (such as the top, bottom, left, right, and middle positions, Such as figure 2 shown), select a test unit for each position;
[0031] Among them, the test unit can be the number of chips that can be pierced by the probe card at one time as a test unit, such as figure 1 As shown, when the upper position of the pr...
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The invention discloses a trimming method. The method includes the step of conducting analysis through technical judgment to find out whether testing units belong to a middle area or a surrounding area of a wafer so that the trimming target value of the middle area and the trimming target value of the surrounding area can be separated. By means of the method, the trimming target values of the testing units belonging to the surrounding area and the trimming target value of the middle area can be independently set, the different characteristics of the two obviously different areas, namely, the periphery and the center of the wafer, are truly taken into consideration, and the trimming target values of all parameters in each area are unified. In addition, when the trimming target values are written in a chip, the parallel writing mode can be adopted instead of the writing mode that the trimming target values are written in series one by one, and the testing time is greatly shortened.
Description
technical field [0001] The invention relates to the field of testing of large-scale integrated circuits, in particular to a chip parameter trimming method. Background technique [0002] When testing existing large-scale integrated circuits, some chip parameters often need to be adjusted. Due to production reasons, the eigenvalues of these parameters are different and need to be adjusted within a certain range. In order to achieve this goal, this feature of some chips requires negative trimming, while others require positive trimming, resulting in inconsistencies in the trimming values of each chip. [0003] However, when large-scale logic testing instruments test chips, from the perspective of production, they often use large-scale simultaneous testing, which is in contradiction with the purpose of the above-mentioned adjustment. In order to balance the two, it is necessary to find a more effective method. Improve the accuracy of trimming while ensuring mass production....
Claims
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IPC IPC(8): H01L21/66G01R31/26
CPCG01R31/2601H01L22/14
Inventor 辛吉升谢晋春
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP