Multiplication of FPGA chip

Abstract

The present invention relates to a multiplier based on an FPGA chip, comprising: a partial product generator, implemented by a first look-up table, for performing an AND operation on each bit of the multiplier and the multiplicand to obtain n items of partial product data , wherein, the first look-up table is selected according to the position of the data of the multiplier and the multiplicand when each bit of the multiplier and the multiplicand are respectively ANDed, so that the aforementioned pair of multipliers and the multiplied The first look-up tables that perform AND operations on each bit in the number are shifted relative to each other, so that the partial product data of n items are shifted; Accumulation processing of partial product data to obtain summation data. In this way, the function of using the addition and carry chain in the FPGA chip to realize the multiplication is realized, and the use of the accumulator constructed based on the optimal binary tree improves the operating efficiency of the entire FPGA chip.

Description

technical field [0001] The invention relates to a multiplier, in particular to a multiplier based on an FPGA chip. Background technique [0002] In FPGA design, multiplication operations are often used. In the FPGA chip architecture, there are usually a large number of carry chains used to implement addition operations. [0003] In the prior art, the research on using the addition and carry chain to realize the multiplication function in the FPGA chip is still in a blank state. When using other methods to realize the multiplication function, the number of serial addition operations of the final product is often too large, resulting in The entire FPGA chip operates inefficiently. Contents of the invention [0004] The purpose of the present invention is to provide a kind of multiplier based on FPGA chip for the defective of prior art, this multiplier can utilize the addition carry chain in the FPGA chip to realize the function of multiplication. [0005] For achieving th...

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Problems solved by technology

[0003] In the prior art, the research on using the addition and carry chain to realize the multiplication function in the FPGA chip is still in a blank state. When using other methods to realize the multiplication function, the number of serial addition operations of the final product is often too large, resulting in The entire FPGA chip operates inefficiently

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