Direct memory access controller, control method thereof, and information processing system

[0040] (First embodiment)

[0041] The first embodiment is described.

[0042] figure 1 Is a diagram showing a configuration example of an information processing system including a direct memory access (DMA) controller according to the first embodiment. Such as figure 1 As shown, the information processing system includes a DMA controller 10, a main CPU (central processing unit) 20, a RAM (random access memory) 30 for the main CPU, a sub CPU 40, a RAM 50 for the sub CPU, and media access Control (MAC) part 60.

[0043] in figure 1 In the information processing system shown, the power consumption of the combination of the sub CPU 40 and the RAM 50 is lower than the power consumption of the combination of the main CPU 20 and the RAM 30. In the normal operation state (normal mode), both the main CPU 20 and the sub CPU 40 are activated. On the other hand, in the standby state (standby mode), the power to the main CPU 20 and RAM 30 as the normal system is cut off so that the main CPU 20 and RAM 30 are stopped, and the sub CPU 40 and RAM 50 as the standby system are executed. deal with. The information processing system is connected to the network via the MAC part 60 and a physical (PHY) part not shown.

[0044] The DMA controller 10 is a descriptor-type DMA controller that performs DMA transfer of data based on the descriptor 31 stored at the RAM 30 and the descriptor 51 stored at the RAM 50. The DMA controller 10 includes a descriptor read/write processing section 102, a data read/write processing section 103, a channel switching section (packet switcher) 104, a mode setting register 105, and a packet data saving buffer 106.

[0045] The DMA controller 10 includes a DMA channel (main CPU channel) 101A for the main CPU and a DMA channel (sub CPU channel) 101B for the sub CPU. That is, the DMA controller 10 according to the present embodiment includes a separate DMA channel for each of the normal system and the backup system.

[0046] The main CPU channel 101A includes a receiving DMA channel 111A and a transmitting DMA channel 121A. Similarly, the sub CPU channel 101B includes a reception DMA channel 111B and a transmission DMA channel 121B.

[0047] Each receiving channel 111A (111B) includes a base address register 112A (112B), a current address register 113A (113B), an end address register 114A (114B), a register 115A (115B) for the number of remaining packets, and a restart processing section 116A (116B) ) And the control section 117A (117B). Each transmission channel 121A (121B) includes a base address register 122A (122B), a current address register 123A (123B), an end address register 124A (124B), a register 125A (125B) for the number of remaining packets, and a restart processing section 126A (126B) ) And the control section 127A (127B).

[0048] The respective functions of the base address register, the current address register, the end address register, the number of remaining packets, the restart processing part and the control part of each channel are the same. Store the first address of the descriptor placed on the corresponding RAM in the base address register. Store the end address of the descriptor placed on the corresponding RAM in the end address register. The address of the descriptor corresponding to the packet to be processed next time is stored in the current address register. The address information of the RAM where the packets are actually arranged, the length information of the packets, and the information used for the processing of the packets are included in this descriptor.

[0049] The register of the number of remaining packets has a function of indicating the number of packets that have not been processed at the DMA channel (the number of remaining packets). The restart processing part has a function of receiving instructions for stopping and starting the DMA channel. When receiving an instruction to stop the DMA channel, the restart processing section stops the transfer processing of packet data belonging to the DMA channel, and executes processing for clearing the descriptor information of the DMA channel. When receiving the instruction for starting the DMA channel, the restart processing section registers the value of the base address register to the current address register, performs processing for clearing the register of the number of remaining packets, and starts the DMA operation. The control part controls the information stored in each register.

[0050] The descriptor read/write processing section 102 performs processing related to the reading and writing of descriptor information. The data read/write processing section 103 performs processing related to data transmitted via the MAC 60. The packet data storage buffer 106 is a buffer that holds packet data received from the network.

[0051] The channel switching section (packet switcher) 104 selects and switches the DMA channel to be used according to the information set at the mode setting register 105. The reception processing section 141 of the channel switching section 104 outputs the received packet data to the selected DMA channel. The transmission packet data from the selected DMA channel is input to the transmission processing section 142 of the channel switching section 104. Information indicating the operation mode of the information processing system (that is, indicating whether the operation mode is a normal operation state (normal mode) or a standby state (standby mode)) is set at the mode setting register 105. Setting this information to the mode setting register 105 is performed by the sub CPU 40.

[0052] The channel switching section 104 has a packet analysis processing function, and performs switching of the DMA channel at the packet boundary according to the information of the mode setting register 105. For example, the information processing system according to this embodiment receives the adoption from the network Figure 2A The data in the shown data format is stored in the received packet buffer 201 as the received packet data 202.

[0053] in Figure 2A In the example, the data format of TCP/IPv4 including the Ethernet header part 203, the IP header part 204, the TCP header part 205, the payload part 206, and the trailer 207 is shown as an example. For example, the data size of the total IP packet can be obtained from the total length field of the IP header part 204, and the TCP header size can be obtained from the data offset field of the TCP header part 205. The data size of the payload part 206 can be acquired based on the data size of the total IP packet acquired from the IP header part 204 and the TCP header size acquired from the TCP header part 205.

[0054] Such as Figure 2B As shown, when a packet is received, the packet header analysis section 211 of the channel switching section 104 extracts the header data of the received packet data 202 from the received packet buffer and analyzes it, and transmits the analyzed header information to the receiving packet processing Part 212. The reception packet processing section 212 acquires the reception packet data from the reception packet buffer based on the header information acquired from the packet header analysis section 211. The received packet processing section 212 extracts payload data from the received packet data, stores the payload data as received payload data 214 to the packet data memory, and sets the packet information at the reception descriptor 213. The channel switching section 104 executes these processes by one grouping unit.

[0055] image 3 It is a flowchart showing an operation example of the channel switching section 104 at the time of packet reception. The channel switching section 104 executes data transfer for the selected DMA channel based on the data size and the like acquired from the information of the header portion of the received packet data until the transmission reaching the packet boundary is completed (S101).

[0056] Upon completion of the transfer reaching the packet boundary (true in S102), when the information set at the mode setting register 105 is information indicating the normal mode (true in S103), the channel switching section 104 selects the main CPU channel 101A ( S104). Subsequently, the channel switching section 104 starts data transfer for one packet from the packet data receiving buffer 106 to the main CPU channel 101A (S105), and the process returns to step S101.

[0057] On the other hand, when the information set at the mode setting register 105 is not information representing the normal mode (ie, information representing the standby mode) (false in S103), the channel switching section 104 selects the sub CPU channel 101B (S106). Subsequently, the channel switching section 104 starts data transfer to the sub CPU channel 101B for one packet from the packet data receiving buffer 106 (S105), and the process returns to step S101.

[0058] In the packet receiving process at the information processing system according to the present embodiment, the packet data is stored in the received packet area on the RAM every time a packet is received. Then according to Figure 4 The shown flowchart distinguishes the presence/absence of packet data on the RAM, and processes the packets one by one. That is, even if a new packet is received during the period from the packet reception to the mode switching process, the packet data is processed in order after saving the packet data in the received packet area on the RAM at any time, and thus the mode switching There is no effect on handling etc.

[0059] Figure 4 It is a flowchart showing packet transfer processing according to this embodiment. When the information processing system detects the transition from the normal mode to the standby mode or the transition from the standby mode to the normal mode (YES in S201), the mode conversion process is performed (S202). Thereafter, when there is a received packet on the RAM (Yes in S203), a receiving packet process is performed (S204), and when there is a transmitting packet on the RAM (Yes in S205), a sending packet process is performed (S206).

[0060] Figure 5 It is a flowchart showing an operation example including mode switching of the information processing system according to the present embodiment. When the operation starts, the sub CPU 40 is activated (S301). Subsequently, the functional part related to the sub CPU (hereinafter referred to as sub DMA) in the DMA controller 10 is reset (S302). After that, the sub DMA in the DMA controller 10 is initialized, the first address of the descriptor on the RAM 50 is registered to the base address registers 112B, 122B (S303), and the sub DMA is activated thereafter (S304).

[0061] Next, the main CPU 20 is activated (S305). Subsequently, the functional part related to the main CPU (hereinafter, referred to as main DMA) in the DMA controller 10 is reset (S306). Thereafter, the main DMA in the DMA controller 10 is initialized, the first address of the descriptor on the RAM 30 is registered to the base address registers 112A, 122A (S307), and after that, the main DMA is activated (S308). The processing from step S301 to step S308 described above is not limited to the processing order shown, and the processing from step S301 to step S304 will be executed in the order shown, and the processing from step S305 to step S308 will be executed in the order shown.

[0062] Next, the sub CPU 40 writes information indicating the normal mode to the mode setting register 105 of the DMA controller 10 (S309). After that, a packet transfer process using the DMA controller 10 is executed (S310). At this time, when the following instruction is received: among them, the switching of the mode setting register 105 is required, that is, the mode switching from the normal mode to the standby mode or from the standby mode to the normal mode (true in S311), the CPU switching process is executed (S312), and the process returns to step S310.

[0063] Image 6 Is shown according to Figure 5 The flowchart of the CPU switching process of the first embodiment shown in. In this CPU switching process, when the mode of the process using the main CPU 20, that is, the mode is the normal mode (true in S401), the main CPU 20 that was stopped before that is activated (S402). Subsequently, the main DMA in the DMA controller 10 is reset (S403). After that, the main DMA in the DMA controller 10 is initialized, the first address of the descriptor on the RAM is reloaded to the base address registers 112A, 122A (S404), and after that, the main DMA is activated (S405).

[0064] The main CPU 20 notifies the sub CPU 40 of the completion of activation (S406). The sub CPU 40 that has received the notification of the completion of activation from the main CPU 20 sets information indicating the normal mode at the mode setting register 105 of the DMA controller 10 (S407). Subsequently, the channel switching section 104 of the DMA controller 10 switches the DMA channel to be used to the main CPU channel 101A according to the information set in the mode setting register 105, notifies the sub CPU 40 of the completion of the mode switching (S408), and completes the CPU switching process .

[0065] On the other hand, if it is not the process using the main CPU 20 (false in S401), the main CPU 20 requests the sub CPU 40 to switch to the standby mode (S409). The sub CPU 40 that has received the request to switch to the standby mode sets information indicating the standby mode at the mode setting register 105 of the DMA controller 10 (S410). Subsequently, the channel switching section 104 of the DMA controller 10 switches the DMA channel to be used to the sub CPU channel 101B according to the information set at the mode setting register 105, and notifies the sub CPU 40 of the mode switching completion (S411).

[0066] Next, the sub CPU 40 that has received the notification of the completion of the mode switching notifies the main CPU 20 of power-off permission (S412). Then, the power to the main CPU 20 and the RAM 30 for the main CPU is cut off (S413), and the CPU switching process is completed.

[0067] According to the first embodiment, the DMA channel 101A for the main CPU and the DMA channel 101B for the sub CPU are each set at the DMA controller 10, and the channel switching section 104 automatically according to the information set at the mode setting register 105 To select the DMA channel to be used, and perform switching to the selected DMA channel at the packet boundary. Thereby, the mode switching can be performed without performing information reset and stopping the DMA operation when performing the mode switching, that is, without interrupting the DMA operation. Therefore, it is possible to realize mode switching without incurring deterioration of communication quality caused by packet loss, and it is possible to enable energy saving by reducing power consumption at the information processing system.

[0068] Note that the DMA channel switching of the channel switching section 104 is the switching of the reference mode setting register 105, and therefore can be performed in a very short period of time (for example, one clock cycle to several clock cycles).

[0069] (Second embodiment)

[0070] Next, the second embodiment is described.

[0071] In the first embodiment described above, at the time of transition from the normal mode to the standby mode, the notification of power-off permission from the sub CPU 40 is received, and the power to the main CPU 20 and RAM 30 for the main CPU is cut off. At this time, there is a possibility that data that has not yet been transmitted remains in the transmission channel 121A of the main CPU channel 101A at the DMA controller 10. The descriptor type DMA controller continues to operate until the descriptor becomes empty, and therefore, when the power to the main CPU 20 and RAM 30 is cut off, data that has not yet been transmitted remains in the transmission channel 121A of the main CPU channel 101A At this time, access to RAM 30 is performed, and a bus access error occurs.

[0072] In order to avoid the occurrence of a bus access error, it is conceivable that the sub CPU 40 resets the transmission channel 121A by using the restart processing section of the main CPU channel before executing the power-off permission notification to the main CPU 20. Thereby, the transmission channel 121A is initialized, and no access to the RAM 3 occurs after the power to the RAM 30 is cut off. However, it is impossible for the sub CPU 40 to recognize the packet boundary of the transmission packet, and therefore, there is a possibility that a damaged packet having an incomplete format is transmitted to the network when the transmission channel 121A is restarted during the transmission process.

[0073] In addition, it is conceivable that the control is performed so that the sub CPU 40 does not perform the notification of the power-off permission to the main CPU 20 until there is no remaining data of the transmission channel 121A of the main CPU channel 101A (until the register 125A of the number of remaining packets Until the value becomes "0" (zero)). However, the timing of the transition from the normal mode to the standby mode is delayed, and power consumption increases.

[0074] The second embodiment described below is an embodiment in which it is ensured that the occurrence of bus access errors is avoided during the transition from the normal mode to the standby mode without incurring the aforementioned problems. Figure 7 Is a diagram showing a configuration example of an information processing system including a DMA controller according to the second embodiment. in Figure 7 Medium, for having and figure 1 The functions of the parts shown in the parts with the same functions use the same reference numerals and signs, and will not be repeated.

[0075] The DMA controller 10 according to the second embodiment includes such Figure 7 The restart timing adjustment section 107 is shown. The restart timing adjustment section 107 receives from the sub CPU 40 a request for execution of restart processing of the transmission channel 121A of the main CPU channel 101A, and requests information for the boundary timing of the transmission packet of the channel switching section 104. The restart timing adjustment section 70 performs the restart of the transmission channel 121A at the boundary timing of the transmission packet based on the information acquired from the channel switching section 104, and notifies the sub CPU 40 of the completion of the restart of the transmission channel 121A.

[0076] Such as Figure 8 As shown, when the packet is transmitted, the packet header generation section 303 of the channel switching section 104 acquires header configuration information for generating the packet header from the transmission descriptor 301, and generates the header. The transmission packet processing section 304 acquires the header data generated by the packet header generation section 303, and acquires the payload data 302 of the transmission packet from the packet data memory indicated by the transmission descriptor 301 to generate the transmission packet. When the generation is completed, the transmission packet processing section 304 transfers the transmission packet to the physical (PHY) section 305. Whenever a packet is transferred to the physical section 305, the transmission packet processing section 304 outputs a processing completion notification to the restart timing adjustment section 107. The channel switching section 104 can recognize the packet boundary when the header of the transmission packet that is the same as the header analysis of the reception packet is generated based on the header information.

[0077] The operation of the information processing system of the second embodiment differs from the operation of the first embodiment in the CPU switching process, while other operations are different from those of the first embodiment. Figure 5 The operation of the first embodiment shown is the same. Picture 9 It is a flowchart showing the CPU switching process in the second embodiment. note, Picture 9 The processing at the time of transition from the normal mode to the standby mode in the CPU switching processing is shown. The processing at the time of transition from the normal mode to the standby mode is the same as that of the first embodiment. And execute Image 6 The processing from step S402 to step S408 is shown.

[0078] In the CPU switching processing of the second embodiment, if it is not processing using the main CPU 20, the main CPU 20 requests the sub CPU 40 to switch to the standby mode (S501). The sub CPU 40 that has received the request to switch to the standby mode sets information indicating the standby mode at the mode setting register 105 of the DMA controller 10 (S502). Subsequently, the channel switching section 104 of the DMA controller 10 switches the DMA channel to be used to the sub CPU channel 101B according to the information set at the mode setting register 105, and notifies the sub CPU 40 of the completion of mode switching (S503).

[0079] The sub CPU 40 that has received the notification of the completion of the mode switching from the channel switching section 104 requests the restart timing adjustment section 107 to execute the restart processing of the transmission channel 121A of the main CPU channel 101A (S504). The restart timing adjustment section 107 requests the channel switching section 104 to notify the information of the boundary timing of the transmission packet (S505). The channel switching section 104 notifies the restart timing adjustment section 107 of the information of the boundary timing of the transmission packet transmitted by the transmission channel 121A (S506).

[0080] Subsequently, the restart timing adjustment section 107 detects the timing for completing the transmission of one packet transmitted through the transmission channel 121A based on the information from the channel switching section 104, and controls the restart processing section 126A of the transmission channel 121A to perform restart at that timing ( S507). Thereby, the transmission channel 121A of the main CPU channel 101A is reset. The restart timing adjustment section 107 notifies the sub CPU 40 that the restart of the transmission channel 121A is completed (S508).

[0081] Next, the sub CPU 40 that has received the notification of the restart completion of the transmission channel 121A notifies the main CPU 20 of the power-off permission (S509). The power to the main CPU 20 and the RAM 30 for the main CPU is cut off (S510), and the CPU switching process is completed.

[0082] According to the second embodiment, as in the first embodiment, mode switching can be performed without the need to stop the DMA operation while performing resetting of information when the mode switching is performed (ie, without interrupting the DMA operation). Therefore, it is possible to realize mode switching without incurring deterioration of communication quality caused by packet loss, and it is possible to enable energy saving by reducing power consumption at the information processing system. In addition, when switching from the normal mode to the standby mode, it is possible to ensure that the occurrence of bus access errors is avoided without incurring problems such as the transmission of damaged packets.

[0083] (Third embodiment)

[0084] Next, the third embodiment is described.

[0085] In the above embodiment, when switching from the normal mode to the standby mode, on the side of the sub CPU, from the time when the instruction indicates that the mode switching from the standby mode to the normal mode is necessary to when the main CPU is activated, the DMA controller 10 When the main DMA is activated and the channel switching to the main CPU channel 101A is completed, the packet from the network is received. It is necessary to transfer the received packet to the main CPU side, and it is conceivable to transfer it through inter-CPU communication. However, if the inter-CPU communication is performed, the control becomes complicated. In addition, it takes time to transfer packet data from the sub CPU side to the main CPU side through inter-CPU communication, and therefore, a deterioration in packet response delay and the occurrence of packet loss are incurred during this period, and there is a possibility that communication quality may deteriorate.

[0086] In the third embodiment, such as Picture 10 The loopback processing section 143 shown in is provided in the DMA controller 10. Picture 10 Is a diagram showing a configuration example of an information processing system including a DMA controller according to the third embodiment. in Picture 10 Medium, for having and figure 1 with Figure 7 The functions of the parts shown in the parts with the same functions use the same reference numerals and signs, and will not be repeated.

[0087] The loopback processing section 143 transfers the packet data transmitted from the transmission channel 121B of the sub CPU channel 101B to the reception channel 111A of the main CPU channel 101A. Note that the control of whether the loopback processing unit 143 is operated can be performed by providing, for example, a loopback mode setting register and the sub CPU 40 that sets information thereof. The control can be performed by setting the register 105 in the extended mode so that information indicating whether to perform loopback can be set.

[0088] The operation of the information processing system according to the third embodiment differs from the operation of the first embodiment in the CPU switching process, but other operations are different from those of the first embodiment. Figure 5 The operation in the first embodiment shown is the same. Picture 11 It is a flowchart showing the CPU switching process according to the third embodiment. Note that in Picture 11 In the CPU switching process, the process at the time of transition from the standby mode to the normal mode is shown. The processing at the time of transition from the normal mode to the standby mode is the same as the processing in the second embodiment, and executes Picture 9 The treatment shown.

[0089] In the switching process of the CPU according to the third embodiment, the main CPU 20 that was stopped is activated when the main CPU 20 is used (ie, the normal mode) (S601). Thereafter, the processing at step S602 to step S607 is the same as Image 6 The processing at step S403 to step S408 in the first embodiment shown is the same, and therefore will not be described.

[0090] After the channel switching section 104 of the DMA controller 10 notifies the sub CPU 40 that the mode switching is completed, the channel switching section 104 selects the loopback by the loopback processing section 143 based on the setting information from the sub CPU 40 through automatic channel allocation (S608), And the transfer of the remaining received packet data is performed (S609). Thus, the packet data is transferred from the RAM 50 for the sub CPU to the RAM 50 for the main CPU via the transmission channel 121B of the sub CPU channel 101B, the loopback processing section 143 of the channel switching section 104, and the reception channel 111A of the main CPU channel 101A. RAM30. When receiving packet data from the network during transmission of the packet data through the loopback, the channel switching section 104 transmits the received packet data from the network to the receiving channel 111B of the sub CPU channel 101B.

[0091] According to the third embodiment, as in the first embodiment, mode switching can be performed without performing resetting of information while performing mode switching while stopping the DMA operation (that is, without interrupting the DMA operation). Therefore, mode switching can be performed without incurring deterioration of communication quality caused by packet loss, and it is possible to enable energy saving by reducing power consumption at the information processing system.

[0092] In addition, according to the third embodiment, a loopback mechanism is provided, and thus, when packet data received on the side of the sub CPU remains at the time of switching from the standby mode to the normal mode, the packet data can be transferred from the one used for the sub CPU. The RAM 50 is transferred to the RAM 30 for the main CPU without performing inter-CPU communication. In addition, on the main CPU side, processing of packet data received through loopback can be executed as if data from the network is received.