High/low-speed bus communication method and device

Abstract

The invention discloses a high / low-speed bus communication method. The method comprises write operation and read operation of a high-speed bus. The write operation comprises the following steps: performing address decoding on high-speed parallel data; allocating a write operation token to a first storage unit, and writing the high-speed parallel data into the first storage unit; converting the high-speed parallel data into low-speed serial data and writing the low-speed serial data into a low-speed bus; and releasing the write operation token. The read operation comprises the following steps: allocating a write operation token to a second storage unit; converting corresponding low-speed serial data into high-speed parallel data, writing the high-speed parallel data into the second storage unit, and writing the high-speed parallel data into the high-speed bus; and releasing a read operation token. The invention also discloses a communication device. The communication device comprises a control logical module, a token partition module, an address decoding module, a series-to-parallel conversion module, a parallel-to-series conversion module and a data buffering module. Both the method and device have the advantages of time division multiplexing, high communication efficiency, high instantaneity and high stability.

Description

technical field [0001] The present invention mainly relates to the technical field of communication, in particular to a high and low speed bus communication method and device. Background technique [0002] In multi-node reconnection communication, the data exchange of high and low speed bus is the key link. In rail transit, mining, metallurgy, and radio communication industries, data exchange between high and low speed buses is involved. This technology has become one of the key criteria to measure whether the performance of the communication system is good or not. At present, the hardware dual-port RAM chip is usually used for data exchange of high and low speed buses, which is relatively expensive, resulting in an increase in hardware costs; in addition, the gate circuit logic of this kind of hardware is complex, and the system stability is poor; the data exchange of high and low speed buses using FPGA is also difficult. It does not support automatic switching of address...

AI Technical Summary

Problems solved by technology

At present, the hardware dual-port RAM chip is usually used for data exchange of high and low speed buses, which is relatively expensive, resulting in an increase in hardware costs; in addition, the gate circuit logic of this hardware is complex and the system stability is poor; the data exchange of high and low speed buses using FPGA is also difficult. Does not support automatic switching of address areas and time-division multiplexing of the bus by multiple nodes

Images