Cache replacement method, cache controller and processor

Abstract

An embodiment of the present invention provides a cache replacement method, a cache controller, and a processor. The method includes: the cache controller determines the associated cache pool of the cache line to be replaced, and associates each associated cache line in the cache pool with the cache line to be replaced. The cache line belongs to the same memory line, and further determines the cache line to be written back from the associated cache pool according to the access information of the associated cache line, and writes the cache line to be replaced and the data in the cache line to be written back to the memory together. Since the cache line to be replaced and the cache line to be written back belong to the same memory line, the hit rate of the line cache can be improved, thereby improving the memory access performance. In addition, the cache controller further selects the associated cache line from the associated cache pool according to the access information of the associated cache line. The cache line to be written back is determined in the cache line, and only the cache line to be written back in the associated cache pool is written back to the memory. Therefore, the number of writes to the memory can be reduced and the service life of the memory can be improved.

Description

technical field [0001] Embodiments of the present invention relate to communication technologies, and in particular, to a cache replacement method, a cache controller, and a processor. Background technique [0002] With the development of big data applications, there are increasingly higher requirements for memory capacity and access speed, and the commonly used Dynamic Random-Access Memory (DRAM) can no longer meet the requirements. A new type of non-volatile memory (Non-Volatile Memory, referred to as NVM) is expected to replace DRAM as a memory system in a computer system due to its advantages of large capacity and low power consumption. However, the read and write latency of existing NVM is higher than that of DRAM, and the number of writes is limited. [0003] The internal read and write mechanism of NVM is similar to that of DRAM. NVM has a row buffer (Row buffer) to save the data in the most recently accessed memory row. The delay of NVM access depends on whether the...

AI Technical Summary

Problems solved by technology

In the existing mechanism, affected by the cache (cache) replacement strategy, the address of the request sent to the memory is relatively random. Therefore, the line buffer hit rate is poor, which affects the memory access performance

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