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Power bouncing reduction circuit and method thereof

An integrated circuit and packaging technology, which is applied in the field of packaged integrated circuit components and their power bounce reduction, can solve the problems of reducing the reliability of integrated circuits 110, expensive packaging circuits, and unsatisfactory power bounce.

Active Publication Date: 2015-12-23
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Power supply bouncing is highly undesirable since power supply bouncing can degrade the reliability of integrated circuit 110
Packaged circuits with lower inductance can be used to alleviate the problem of power supply bounce; however, packaged circuits with lower inductance are usually quite expensive

Method used

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  • Power bouncing reduction circuit and method thereof
  • Power bouncing reduction circuit and method thereof
  • Power bouncing reduction circuit and method thereof

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Embodiment Construction

[0018] The following detailed description refers to the accompanying drawings, and discloses various practicable embodiments of the present invention by way of illustration. The described embodiments are definite and sufficiently disclosed to enable those of ordinary skill in the art to implement them. Different embodiments are not mutually exclusive, some embodiments can be combined with one or more embodiments to form new embodiments. Therefore, the following detailed description is not intended to limit the invention.

[0019] figure 2 It is a functional block diagram of a packaged integrated circuit device according to an embodiment of the present invention. refer to figure 2 A packaged integrated circuit (IC) device 200 includes a core circuit 210 , a packaged circuit 220 and a power bounce reduction circuit 230 . The core circuit 210 is coupled to the first external power supply node 203 via the packaging circuit 220 . Here, the encapsulation circuit 220 is couple...

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PUM

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Abstract

A circuit having a core circuit for sinking a first current from a first internal power supply node; a power bouncing reduction circuit for receiving power from a second internal power supply node and sourcing a second current to the first internal power supply node in accordance with a comparison between a voltage at the first internal power supply node and a low-pass filtered voltage of the first internal power supply node; and a package for coupling the first internal power supply node and the second internal power supply node to a first external power supply node and a second external power supply node, respectively.

Description

technical field [0001] The present invention relates to an integrated circuit, in particular to a packaged integrated circuit (IC) assembly and a method for reducing power supply bounce. Background technique [0002] Those skilled in the art should understand various terms and basic concepts related to microelectronics used in the specification, such as: P-type metal-oxide semiconductor (p-channelmetal-oxide semiconductor; PMOS) transistor, N-type metal-oxide semiconductor (n-channelmetal-oxidesemiconductor; NMOS) transistor, "inductance", "capacitance", "resistance", "voltage", "current", "current source", "circuit node", "low-pass filter (low-pass filter) ;LPF)", "Preamplifier", "Comparator", "Frequency" and "Latch". These terms and basic concepts can be obvious from prior art documents such as textbooks, so they will not be defined or explained in the specification. Among them, the textbook can be, for example: Design of Analog CMOS Integrated Circuits (Design of Analog...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/1254
CPCG05F3/02G06F1/26H03K19/00369
Inventor 林嘉亮
Owner REALTEK SEMICON CORP