sram storage unit and storage array

Abstract

The invention relates to a SRAM storage unit and a storage array. The SRAM storage unit includes: a first double-gate PMOS transistor, a second double-gate PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first pass transistor, a second pass transistor and a compensation unit. The invention can overcome the single event inversion effect of the SRAM storage unit.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an SRAM storage unit and a storage array. Background technique [0002] SRAM (Static Random Access Memory, hereinafter referred to as SRAM) has the advantages of high speed, low power consumption and compatibility with standard processes. It is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia players) and other fields. [0003] The most common SRAM storage unit is 6T unit, such as figure 1 As shown, the SRAM storage unit includes: a first PMOS transistor ML0, a second PMOS transistor ML1, a first NMOS transistor MPD0, a second NMOS transistor MPD1, a third NMOS transistor MPG0 and a fourth NMOS transistor MPG1. [0004] The first PMOS transistor ML0 , the second PMOS transistor ML1 , the first NMOS transistor MPD0 and the second NMOS transistor MPD1 form a bistable circuit, and the bistable circuit forms a latch ...

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Problems solved by technology

[0021] Similarly, if charged particles bombard the storage node N0, the same consequences will be caused

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