SRAM storage unit and SRAM storage array

Abstract

The invention relates to an SRAM (Static Random Access Memory) storage unit and an SRAM storage array, wherein the SRAM storage unit comprises a first double-grid PMOS (P-channel Metal Oxide Semiconductor) transistor, a second double-grid PMOS transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, a second NMOS transistor, a first transmission transistor, a second transmission transistor and a compensation unit. The SRAM storage unit and the SRAM storage array have the advantage that the event upset effect of the SRAM storage unit can be overcome.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to an SRAM storage unit and a storage array. Background technique [0002] Static Random Access Memory (SRAM) has the advantages of high speed, low power consumption and compatibility with standard processes. It is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia players) and other fields. [0003] The most common SRAM storage unit is 6T unit, such as figure 1 As shown, the SRAM storage unit includes: a first PMOS transistor ML0, a second PMOS transistor ML1, a first NMOS transistor MPD0, a second NMOS transistor MPD1, a third NMOS transistor MPG0, and a fourth NMOS transistor MPG1. [0004] The first PMOS transistor ML0, the second PMOS transistor ML1, the first NMOS transistor MPD0, and the second NMOS transistor MPD1 constitute a bistable circuit, and the bistable circuit forms a latch for latching data information....

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Problems solved by technology

[0021] Similarly, if charged particles bombard the storage node N0, the same consequences will be caused

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