A calibration module and calibration method for clock mismatch error of tiadc system

Abstract

The invention discloses a calibration module for TIADC system clock mismatch errors and a calibration method. The invention is characterized in that the calibration module comprises a delay module, a subtractor module, a clock sampling module, an error judgment module and a variable delay line module; a sampling clock signal of a first sub channel ADC as a reference clock signal, a clock calibration module is disposed between a sampling clock signal of each of other M-1 sub channel ADC and the corresponding sampling hold circuit of each of the M-1 sub channel ADC; and in this way, the M-1 clock calibration modules constitute the calibration module. The invention is suitable for calibration of a TIADC system of any number of channels and for signals in the entire Nyquist sampling frequency, can be used for easily obtaining the clock mismatch errors of each channel and performing efficient compensation, and therefore achieve the calibration of TIADC clock mismatch errors quickly and accurately with less hardware spending.

Description

technical field [0001] The invention relates to the field of analog-to-digital conversion, in particular to a multi-channel time-interleaved analog-to-digital converter clock mismatch error calibration module and a calibration method thereof. Background technique [0002] With the wide application of digital signal processing technology in medical equipment, communication, consumer electronics and other fields, the analog-to-digital converter as a bridge between the analog world and the digital world is particularly important. However, with the development of deep submicron CMOS technology towards lower power supply voltage and smaller feature size, the design of high-precision, high-speed analog-to-digital converters using traditional structures will become more and more difficult. [0003] The multi-channel time-interleaved ADC can break through the limitation brought by process factors through parallel acquisition technology, so that the speed of the analog-to-digital con...

AI Technical Summary

Problems solved by technology

Calibration of clock mismatch errors based on correlation-based algorithms proposed by S.Jamal and D.Fu (A 10-b 120-Msample / s time-interleaved analog-to-digital converter with digitalbackground calibration) , but this scheme is only applicable to two-channel TIADC, and cannot be expanded to more channels or even any channel

Chung-Yi Wang and Jieh-Tsorng Wu et al proposed to do zero detection between channels to extract the clock mismatch error between channels (“A Background Timing-Skew Calibration Technique for Time-Interleaved Analog-to-Digital Converters” Chung-Yi Wang, Student Member, IEEE, and Jieh-Tsorng Wu, Member, IEEE), however, this scheme has limitations on the frequency of the input signal, and the calibration effect is not ideal at high frequencies

Roger Petigny and Hugo Gicquel et al. proposed to add a reference channel with a sub-channel accuracy similar to that of TIADC for calibration ("Background Time Skew Calibration for Time-InterleavedADC Using Phase Detection Method"). However, the requirements of this scheme for the reference channel are relatively High, high hardware consumption

Arash Shahmansoori et al proposed to use DTFT filtering to calibrate the clock mismatch error ("Consecutive adaptive blind estimation of timing offsets for arbitrary channel time-interleaved ADCs"), but this scheme can only calibrate the clock mismatch error of each channel sequentially, Calibration rate is low

Images