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Array substrate, manufacturing method thereof, and liquid crystal display panel

A technology of array substrates and substrates, which is applied in the direction of instruments, nonlinear optics, optics, etc., can solve problems such as affecting electrical connections and disconnections, and achieve the effects of increasing structural strength, preventing disconnections, and ensuring electrical connections

Active Publication Date: 2018-09-18
TCL CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

The stepped structure usually has (Angstrom) height difference, and the source and drain of the current thin film transistor are generally designed to be thinner and narrower due to the need to ensure the pixel aperture ratio, so it is very easy to break the line at the step structure, affecting its connection with the corresponding signal Electrical connection of traces

Method used

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  • Array substrate, manufacturing method thereof, and liquid crystal display panel
  • Array substrate, manufacturing method thereof, and liquid crystal display panel
  • Array substrate, manufacturing method thereof, and liquid crystal display panel

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Embodiment Construction

[0021] The following will clearly and completely describe the technical solutions of the exemplary embodiments provided by the present invention with reference to the accompanying drawings in the embodiments of the present invention.

[0022] figure 1 is a structural cross-sectional view of an embodiment of the array substrate of the present invention. Such as figure 1 As shown, the array substrate 10 includes a substrate 11 , an insulating layer 12 , a semiconductor pattern (layer) 13 , a metal wiring layer 14 , a first passivation layer 15 and a conductive layer 16 .

[0023] Wherein, the insulating layer 12 and the semiconductor pattern 13 are sequentially formed on the substrate 11; the metal wiring layer 14 is formed on the insulating layer 12 and the semiconductor pattern 13; the first passivation layer 15 is formed on the metal wiring layer 14 and the first passivation layer 15 is formed with a first contact hole O 1 , the first contact hole O 1 exposing a part of t...

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Abstract

The invention provides an array substrate. The array substrate comprises: an insulation layer and a semiconductor pattern which are successively formed on a substrate; a metal wiring layer formed on the insulation layer and the semiconductor pattern; a first passivation layer which is formed on the metal wiring layer and forms a first contact hole exposing the metal wiring layer disposed at the edge of the semiconductor pattern; and a conductive layer which is formed on the first contact hole and covers the metal wiring layer exposed by the first contact holes. The invention further provides a manufacturing method of the array substrate, and a liquid crystal display panel. According to the invention, line breaking at the source electrode and the drain electrode of a thin film transistor can be prevented, electrical connection with corresponding signal lines is ensured, and the aperture rate is improved.

Description

technical field [0001] The present invention relates to the technical field of liquid crystal display, in particular to an array substrate, a manufacturing method thereof, and a liquid crystal display panel. Background technique [0002] In the structure of the current liquid crystal display (Liquid Crystal Display, LCD) array substrate, the gate of the thin film transistor is disposed on the substrate, resulting in the gate insulating layer formed on the gate having a highly uneven layer structure, that is, the gate The electrode insulating layer includes a first region with a higher height above the gate and a second region with a smaller height corresponding to the outer periphery of the gate, so that the semiconductor pattern layer formed on the gate insulating layer corresponds to the first region and the second region. The junction of the two regions has a step structure, which further causes the source and drain formed on the semiconductor pattern layer to also have a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G02F1/1362G02F1/1333
CPCG02F1/1333G02F1/136227G02F1/136286
Inventor 黄秋平
Owner TCL CHINA STAR OPTOELECTRONICS TECH CO LTD
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