Vertical device architecture

Abstract

The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate. A channel region with one or more vertical channel bars is disposed over the source region. The one or more vertical channel bars have a bottom surface abutting the source region that has a rectangular shape (i.e., a shape with four sides, with adjacent sides of different length, and four right angles). A gate region is located over the source region at a position abutting the vertical channel bars, and a drain region is disposed over the gate region and the vertical channel bars. The rectangular shape of the vertical channel bars provides for a vertical device having good performance and cell area density.

Description

technical field [0001] The present invention relates generally to the field of semiconductor technology, and more particularly, to vertical transistor devices and methods of forming the same. Background technique [0002] Moore's Law states that the number of transistors in an integrated circuit doubles approximately every two years. To realize Moore's Law, the integrated chip industry continues to reduce the size (ie, scale) of integrated chip components. In recent years, however, scaling has become more difficult as the physical limits of the materials used in the fabrication of integrated chips are approached. Therefore, as an alternative to traditional scaling, the semiconductor industry has turned to alternative technologies (eg, FinFETs) to continue to satisfy Moore's Law. [0003] An alternative to conventional silicon planar field effect transistors (FETs) that has recently emerged is nanowire transistor devices. Nanowire transistor devices use one or more nanowir...

AI Technical Summary

Problems solved by technology

In recent years, however, scaling has become more difficult as the physical limits of the materials used in the fabrication of integrated chips are being approached

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