Unlock instant, AI-driven research and patent intelligence for your innovation.

Integrated circuit for storing data

A technology for integrated circuits and data storage, which is applied in information storage, static memory, digital memory information, etc., and can solve problems such as adverse effects on reliability

Active Publication Date: 2016-03-02
SYNOPSYS INC
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But at higher voltage operation, the voltage boost through the write assist circuit will cross the maximum allowable technology voltage and will pass the bit cell gate oxide t ox adverse effects on reliability such as hot carrier injection and insulation breakdown over time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Integrated circuit for storing data
  • Integrated circuit for storing data
  • Integrated circuit for storing data

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] figure 1 An integrated circuit 1 for storing data is shown, the integrated circuit 1 comprising an array of memory cells 100 of column multiplexed SRAM architecture. Memory cell array 100 includes bit cells BC1 , BC2 , . . . , BCn arranged in columns C1 , C2 , . . . , Cn and rows R0 , . The bit cells may be configured as SRAM cells operatively connected to respective word lines WL_0, . . . , WL_TOP and complementary pair of bit lines, figure 1 Only one of the bit lines BL1, BL2, . . . , BLn is shown in . Each bit cell arranged in a common row is connected to a common word line.

[0026] can be achieved by means of the column address signal CA generated by the column address decoder 200 and by figure 1 A row address signal RA generated by a row address decoder not shown in , selects one of the bit cells for a read access or a write access. In order to select one of the bit cells in one of the row R0, ..., RTOP and the column C1, ..., Cn, all the bit cells connected t...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An integrated circuit (10) for storing data comprises a memory cell array (100) comprising a plurality of bit cells (BC1, ..., BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit (10) uses a two-phase write scheme to improve the write-ability in low operating voltage environment.

Description

technical field [0001] The invention relates to an integrated circuit for storing data which can operate at a low operating voltage. The invention also relates to a memory device operating in a low operating voltage environment and a method for operating an integrated circuit for storing data. Background technique [0002] Scaling techniques enable the integration of more functions on a single die, increasing dynamic power and leakage. Today's battery-operated portable devices require low power for a system-on-chip (SOC). Dynamic voltage and frequency scaling is the most effective method for reducing power in SOC designs with lower operating voltages and lower operating frequencies. Integrated circuits for storing data, including arrays of memory cells having bit cells with a static random access memory (SRAM) architecture, are an important part of most SOC designs. [0003] A lower operating voltage (VDDMIN) reduces overdrive voltage in the memory cell array. Shrinking ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/413
CPCG11C7/227G11C8/08G11C2207/229G11C11/419G11C11/418
Inventor 苏尔坦·M·西迪基赛伦德拉·沙拉德赫曼特·瓦茨阿米特·哈努娅
Owner SYNOPSYS INC