A test structure for testing metal connectivity of a wafer stack structure

Abstract

The invention relates to a test structure for testing metal connectivity of a wafer lamination structure. The wafer lamination structure comprises a bottom wafer 201 and a top wafer 202 which is arranged on the bottom wafer and connected with the bottom wafer as a whole. The test structure comprises multiple first vertical interconnection pieces which penetrate through the top wafer 202, multiple first transverse interconnection pieces which are arranged at one side of the upper surface of the top wafer 202, and multiple second transverse interconnection pieces which are arranged at one side of the upper surface of the bottom wafer. The first transverse interconnection pieces and the second transverse interconnection pieces are arranged in an alternating way in a transverse direction. The two adjacent first vertical interconnection pieces are electrically connected at the top part by the first transverse interconnection pieces. The two adjacent first vertical interconnection pieces are electrically connected at the bottom part by the second transverse interconnection pieces. Advantages of the test structure for testing metal connectivity of the wafer lamination structure are that connection degree of stability of the whole loop interface can be quantified by the detection structure.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to a test structure for testing the metal connectivity of a wafer stack structure and a test structure for testing the electromigration and reliability of a connection interface in a wafer stack structure Detect structure. Background technique [0002] In the field of electronic consumption, multi-function devices are more and more popular among consumers. Compared with devices with simple functions, the production process of multi-function devices will be more complicated, such as the need to integrate multiple chips with different functions on the circuit board, so 3D integrated circuit (integrated circuit, IC) technology, 3D integrated circuit (integrated circuit, IC) is defined as a system-level integration structure, stacking multiple chips in the vertical plane direction, thereby saving space, the edge part of each chip Multiple pins can be drawn out as ne...

AI Technical Summary

Problems solved by technology

[0004] In MEMS products, the process of wafer bonding is often used, and the technology of through-silicon vias (TSV) is usually introduced in this process, which brings a new challenge to the stack wafer. That is, the connectivity problem between the various interfaces, the failure of the connection between the stack wafers will directly lead to a decrease in the yield of the device

[0005] In addition, under long-term working conditions, semiconductor devices sometimes fail suddenly, and it is found through detection that electromigration (EM) occurs at the connection between the redistribution layer (RDL) and the through-silicon via TSV, resulting in failure of the circuit connection

[0006] At present, the semiconductor devices of 3D stack wafer (stack wafer) face the reliability problem of multiple connection interfaces (Interface). At present, most of the detection methods are to find out through hot spot analysis (Hot Spot) and slicing after the device fails. Broken interface, but said method takes a lot of time

[0007] The currently used independent test structure (Testkey) can only test the EM phenomenon of each interface in a single way, which cannot reflect the overall situation of the combination; or can only monitor a part of the structure, and cannot test the entire connection system

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