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Method and circuitry for on-chip electro-static discharge protection scheme

An electrostatic discharge and integrated circuit technology, applied in the field of electrostatic discharge protection solutions

Active Publication Date: 2016-05-11
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, providing effective on-chip electrostatic discharge (ESD) protection is challenging for multiple bidirectional input pins with limited die area

Method used

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  • Method and circuitry for on-chip electro-static discharge protection scheme
  • Method and circuitry for on-chip electro-static discharge protection scheme
  • Method and circuitry for on-chip electro-static discharge protection scheme

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Embodiment Construction

[0011] discussed below Figures 1 to 3 And the various embodiments used to describe the principles of the invention in this patent document are done by way of illustration only and should in no way be construed as limiting the scope of the invention in any way. Those skilled in the art will understand that the principles of the present invention may be implemented in any power system.

[0012] The gate driver is a power amplifier that accepts a low power input from the controller IC and is a high power transistor (such as, but not limited to, an insulated gate bipolar transistor (IGBT) or a power metal oxide semiconductor field effect transistor (MOSFET)) The gate generates a high current drive input. Gate drivers may be provided on-chip or as discrete modules. The gate driver may include a level shifter in combination with an amplifier. The isolated gate electrode of the MOSFET forms a capacitor (gate capacitor) that must be charged or discharged whenever the MOSFET is swi...

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PUM

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Abstract

The invention relates to a method and a circuitry for an on-chip electro-static discharge protection scheme. An apparatus includes an integrated circuit (100), a plurality of bi-directional pins (114-116), and an electro-static discharge (ESD) clamp (222). The integrated circuit is configured to provide a ground potential (224). The plurality of bi-directional pins (114-116) are configured to provide a differential input signal for the integrated circuit (100). The electro-static discharge (ESD) clamp (222) is coupled between the ground potential (224) and the plurality of bi-directional pins (114-116).

Description

technical field [0001] The present invention is generally directed to an electrostatic discharge protection scheme. Background technique [0002] The gate driver integrated circuit (IC) receives the control signals and drives the power metal oxide semiconductor field effect transistor (MOSFET). Traditional gate driver ICs typically support a wide positive operating voltage range (ie, -0.3v to 40v) for the input pins. In many applications, system-level clamping / protection devices are used on input pins to address reliability issues in the negative direction of operation due to the voltage difference between control ground and power ground. [0003] A new generation of gate driver ICs incorporates the capability of a bidirectional operating range (ie, -7v to 40v) on the input pin to eliminate system-level clamping devices. Overall system cost is reduced due to fewer devices, lower power loss, and smaller board area. However, providing effective on-chip electrostatic dischar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L21/70
CPCH01L21/70H01L27/0207H01L27/0255
Inventor 陈忠朱丹阳马壮
Owner TEXAS INSTR INC