CTLE value traversal optimization method and device

An optimization method and a technology for optimizing devices, which are applied in the electronic field and can solve problems such as low work efficiency and time-consuming

Inactive Publication Date: 2016-05-11
INSPUR BEIJING ELECTRONICS INFORMATION IND
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Problems solved by technology

[0005] The purpose of the present invention is to provide a CTLE value traversal optimization method and device to solve

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  • CTLE value traversal optimization method and device
  • CTLE value traversal optimization method and device
  • CTLE value traversal optimization method and device

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Embodiment Construction

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0034] see figure 1 , which shows a flowchart of a CTLE value traversal optimization method provided by an embodiment of the present invention, the method is implemented based on BERTscope, and the CTLE value traversal optimization method may include the following steps:

[0035] S11: Read the currently set CTLE value through the CSII software, and use the currently set CTLE value to calculate the bit error rate of the receiver.

[0036] Wherein, the CSII sof...

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Abstract

The invention discloses a CTLE value traversal optimization method and a CTLE value traversal optimization device, which are achieved based on BERTscope. The CTLE value traversal optimization method comprises the steps of reading a currently set CTLE value via CSII software, and computing the bit error rate of a receiver by using the currently set CTLE value; judging whether the bit error rate accords with a preset requirement, if no, modifying the currently set CTLE value by using the CSII software, thus obtaining the currently set CTLE value, and computing the bit error rate of the receiver by using the currently set CTLE value until the bit error rate accords with the preset requirement. According to the CTLE value traversal optimization method, the test of the bit error rate of the receiver is achieved based on BERTscope, and meanwhile the CTLE value is modified via the CSII software, thus the problem that in the prior art the optimization of the CTLE value needs to consume a lot of time and is relatively low in work efficiency is solved.

Description

technical field [0001] The present invention relates to the field of electronic technology, and more specifically, to a CTLE value traversal optimization method and device. Background technique [0002] Faced with the demand for faster and faster data transmission speeds, the transmission speed of high-speed buses continues to increase, such as PCIE3.0, SATA3.0, USB3.0, etc., but in order to ensure the transmission quality of high-speed buses, the corresponding bus associations The signal integrity test requirements related to transmission and reception are required. The test requirement for the receiver is usually BER (Bitter error rate, bit error rate), that is, the bit error rate of the receiver is required to be within a certain range. [0003] Specifically, in order to enhance the quality of the signal, PCIE (Peripheral Component Interface Express, bus and interface standard) uses CTLE (Continuous timeline equalization) technology in the receiver, and the CTLE value cor...

Claims

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Application Information

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IPC IPC(8): H04L25/03
CPCH04L25/03082H04L25/03885
Inventor 钱身飞廖祺
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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