A Multi-mode Adaptive Switching Processor

Abstract

The invention discloses a multimode adaptive switching processor, for solving the problem that the processor compromises and balances high throughput, low power consumption and high reliability. The multimode adaptive switching processor disclosed by the invention is composed of an instruction pool, a first data cache, a first decoupling cache, a computing pool, a second decoupling cache, a storage pool and an adaptive control module, wherein the instruction pool is composed of a high speed instruction cache, a decoding unit and a dispatch unit; the first decoupling cache is composed of 3 instruction caches; the computing pool is composed of 3 groups of computing units; the second decoupling cache is composed of 3 data caches; the storage pool is composed of 3 sub-register files and 3 sub-data memories; and the adaptive control module is software, and sends different switch signals to the dispatch unit, the first data cache, the computing pool and the storage pool according to environmental parameters to change the dispatch strategy of the dispatch unit and achieve adaptive switch of three modes of throughput-power consumption-reliability, so that the processor achieves dynamic optimal overall efficiency in the three modes.

Description

technical field [0001] The present invention mainly relates to reconfigurable processor structure in computer architecture. Background technique [0002] The development trend of highly reliable systems in a specific field is the collaborative design and optimization of throughput, power consumption, and reliability. This new research field has attracted great attention from the industry, and some preliminary research has been carried out. The relevant research mainly focuses on cache Fault tolerance and power balance, such as the article "Dynamic adaptation for fault tolerance and power management in embedded real time system" published by Ying Zhang and Krishnendu H in ACM Trans on Embedded Computing Systems (Dynamic Adaptation for Fault Tolerance and Power Management in Embedded Real Time System Adaptation) and Burleson W and Maheshwari R in IEEE Trans.VLSI Systems "Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits" The tra...

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Problems solved by technology

[0003] The technical problem to be solved by the present invention is: to solve the problem that the existing processors for specific fields cannot effectively compromise and balance between high throughput, low power consumption and high reliability, and propose a process that can perform throughput processing for specific application scenarios. The processor structure of the three modes of rate-power-reliability adaptive switching can adaptively adjust the throughput rate, power consumption and reliability of the processor, so that the overall performance of the processor in these three modes can be dynamically optimized

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