A data-dependent thread grouping mapping method for many-core systems
A technology of data correlation and mapping method, applied in the direction of resource allocation, multi-programming device, etc., can solve the problems of limited versatility, inability to objectively reflect the characteristics of data correlation, and inability to meet the high-performance computing requirements of many-core systems, etc. To achieve the effect of reducing access conflicts, reducing data transmission overhead, and minimizing data dependencies
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Publication Date
- 2019-10-18
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Abstract
Description
Technical field
[0001] The invention belongs to the field of computer system structure and relates to a thread grouping mapping method, in particular to a thread grouping mapping method based on data correlation for many-core systems.
Background technique
[0002] How to make full use of the high computing power of many-core processors and reduce system energy consumption is a key issue faced by many-core systems. With the development of multi-core / many-core technology, more and more processor cores are integrated in many-core processors, which further intensifies the contention among multiple processing cores for on-chip shared computing resources (such as shared cache and shared bandwidth). At the same time, since the many-core processor adopts a multi-level hierarchical storage structure, its storage access is more complicated. If the task allocation is unreasonable during the running of the program, allocating the threads with frequent information interaction to the...
Examples
Embodiment Construction
[0031] The present invention is described in further detail below in conjunction with accompanying drawing:
[0032] see figure 1 , the present invention comprises the following steps:
[0033] 1) According to the maximum number of hardware threads supported by the many-core processor, the application program is divided into a corresponding number of logical threads;
[0034] 2) Use the Intel Pin API to write the Pin tool, and count the storage access data of each thread in parallel;
[0035] 3) The statistics of thread data access information is realized by inserting nodes in the binary tree. The insertion of data nodes adopts a balanced binary tree mid-order insertion algorithm with data timestamps (timestamps representing the order in which data is accessed) as the primary key.
[0036] 4) When inserting a node, record the relevant data item information in the data structure of the node. The node data structure is defined as follows: Node(TS; Element; Frequency; Weight; ...