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Fabrication method of wafer-level uniaxially strained ge on sin buried insulating layer based on amorphization and scale effect

A technology of uniaxial strain on an insulating layer, which is applied in the field of microelectronics, can solve problems such as poor compatibility, excessive mechanical bending, and poor reliability, so as to improve carrier mobility, increase strain, and reduce costs. low effect

Active Publication Date: 2019-01-29
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] This method has the following disadvantages: 1) Poor compatibility with traditional integrated circuit technology: in order to obtain Ge wafers on SiN buried insulating layers with different strains, it needs to additionally manufacture corresponding bending stages with different radii of curvature, and the produced Bending table needs to be compatible with existing annealing equipment
2) Poor reliability: This process requires the use of pressure rods to apply mechanical force to bend the Ge wafer on the SiN buried insulating layer, which will introduce defects in the top layer of germanium; if the Ge wafer on the SiN buried insulating layer is too curved, chipping
3) Due to the fear of breaking the Ge wafer on the SiN buried insulating layer, the bending degree of the mechanical bending cannot be too large, which limits the amount of strain introduced in the top layer of germanium, and the amount of strain that can be achieved is small

Method used

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  • Fabrication method of wafer-level uniaxially strained ge on sin buried insulating layer based on amorphization and scale effect
  • Fabrication method of wafer-level uniaxially strained ge on sin buried insulating layer based on amorphization and scale effect
  • Fabrication method of wafer-level uniaxially strained ge on sin buried insulating layer based on amorphization and scale effect

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Experimental program
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Effect test

Embodiment 1

[0041] Embodiment 1, making a wafer-level uniaxial tensile strain Ge material on a 3-inch SiN buried insulating layer.

[0042] Step 1: Select a 3-inch Ge-on-SiN buried insulating layer wafer and clean it.

[0043] (1a) Alternately ultrasonically clean the Ge wafer on the selected SiN buried insulating layer with acetone and isopropanol to remove organic contamination on the substrate surface;

[0044] (1b) Mix ammonia water, hydrogen peroxide, and deionized water in a ratio of 1:1:3 to form a mixed solution, and heat it to 120°C. Place the Ge wafer on the SiN buried insulating layer in the mixed solution for 12 minutes, and take it out. Rinse with a large amount of deionized water to remove inorganic pollutants on the surface of the Ge wafer on the SiN buried insulating layer;

[0045] (1c) Soak the Ge wafer on the SiN buried insulating layer with HF acid buffer for 2 minutes to remove the oxide layer on the surface.

[0046] Step 2: Deposit SiO 2 Layer 4, such as figure...

Embodiment 2

[0073] Embodiment 2, making a wafer-level uniaxial tensile-strained Ge material on a 4-inch SiN buried insulating layer.

[0074] Step 1: Select Ge on the 4-inch SiN buried insulating layer and clean it.

[0075] The implementation of this step is the same as step 1 of Embodiment 1.

[0076] Step 2: Take out Ge on the cleaned SiN buried insulating layer, and deposit SiO on the top Ge layer 1 by plasma enhanced chemical vapor deposition PECVD process 2 layer, that is, the SiH 4 The flow rate is 45sccm, N 2 O flow is 164sccm, N 2 The flow rate is 800sccm, the gas pressure is 600mTorr, the power is 60W, and the deposition temperature is 300°C, and the SiO with a thickness of 14nm is deposited. 2 Layer 4, such as figure 2 (b) shown.

[0077] Step 3: Use an ion implanter to implant a dose of 6E15cm into the top Ge layer 1 -2 , the energy is 75keV, C ions to form an amorphized layer 5 inside the top Ge layer 1, such as figure 2 (c) shown.

[0078] Step 4: Add SiO 2 Soak ...

Embodiment 3

[0088] Embodiment 3, making a wafer-level uniaxial compressively strained Ge material on an 8-inch SiN buried insulating layer.

[0089] Step A: select an 8-inch Ge wafer on SiN buried insulating layer, and clean it.

[0090] The implementation of this step is the same as step 1 of Embodiment 1.

[0091] Step B: Deposit SiO 2 Layer 4, such as figure 2 (b) shown.

[0092] Take out the Ge wafer on the SiN buried insulating layer after cleaning, and deposit SiO with a thickness of 18nm on the top Ge layer 1 by plasma enhanced chemical vapor deposition PECVD process. 2 Layer 4, such as figure 2 (b) shown.

[0093] The deposition process is as follows: SiH 4 The flow rate is 45sccm, N 2 O flow is 164sccm, N 2 The flow rate is 800 sccm, the gas pressure is 600 mTorr, the power is 60 W, and the deposition temperature is 300° C.

[0094] Step C: forming an amorphized layer 5, such as figure 2 (c) shown.

[0095] Form SiO 2 After layer 4, a dose of 1.4E16cm was applied t...

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Abstract

The invention discloses an amorphization and scale effect-based manufacturing method of wafer-level uniaxial strain Ge on an SiN buried insulating layer. The method comprises the implementation steps of: depositing an SiO2 layer on a top Ge layer of a cleaned Ge wafer on the SiN buried insulating layer; carrying out ion implantation on the top Ge layer to form an amorphous layer and removing the SiO2 layer on the amorphous layer; depositing a tensile stress SiN thin film or a compressive stress SiN thin film on the top Ge layer, etching the SiN thin film into a uniaxial tensile stress SiN strip array or a uniaxial compressive stress SiN strip array, annealing the wafer, recrystallizing the amorphous layer and making the SiN buried insulating layer plastically deform; and etching away the SiN strip array and obtaining the wafer-level uniaxial strain Ge on the SiN buried insulating layer. According to the manufacturing method, the strain capacity of the top Ge layer is high and the manufacturing method can be used for manufacturing the wafer-level uniaxial strain Ge material on the SiN buried insulating layer.

Description

technical field [0001] The invention belongs to the field of microelectronics technology, and relates to semiconductor material manufacturing technology, in particular to a method for manufacturing wafer-level uniaxially strained Ge on a SiN buried insulating layer, which can be used for manufacturing ultra-high-speed, high-temperature, high-power consumption, and high-power integration High-performance GeOI wafers required for circuits and optoelectronic integrated circuits. Background technique [0002] The carrier mobility of traditional bulk Si materials is difficult to meet the needs of future high-performance semiconductor devices and circuits. [0003] The electron and hole mobility of the semiconductor Ge are 2.8 times and 4.2 times that of Si, respectively, and its hole mobility is the highest among all semiconductors. Ge is also an excellent optoelectronic material, and has a wide range of applications in visible light to near-infrared detectors, modulators, optic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/318H01L21/324
CPCH01L21/0217H01L21/02274H01L21/324H01L21/7624
Inventor 戴显英祁林林郝跃底琳佳苗东铭梁彬焦帅
Owner XIDIAN UNIV