Processor of shared storage data, and chip

Abstract

The embodiment of the invention provides a processor of shared storage data, and a chip. The processor comprises a shared storage cell, a controller, a first cluster and a second cluster, wherein the first cluster comprises a first processor core, and the second cluster comprises a second processor core; the shared storage cell is positioned between the first cluster and the second cluster and can be connected with the first processor core or the second processor core through a bus; the controller is connected with the first processor core and the second processor core through the bus and is used for controlling the first processor core to write data generated by the first processor core into the shared storage cell; the shared storage cell is used for storing the data generated by the first processor core; and the controller is also used for controlling the second processor core to read the data which is stored by the shared storage cell and is generated by the first processor core. According to the embodiment of the processor and the chip, the shared storage cell and the controller are additionally provided so that the time for accessing the data in a memory by clusters can be shortened.

Description

technical field [0001] The present invention relates to the field of processors, and more particularly, to a processor and a chip that share stored data. Background technique [0002] Since the 1960s, processor performance has followed Moore's Law and continued to develop at a high speed. With the increasing integration of single-chip transistors, problems such as chip power consumption, line transmission delay, and leakage current are becoming more and more serious. It is very difficult to improve processor performance simply by increasing the main frequency. The rate of return for exploiting instruction-level parallelism is also getting lower and lower. The development of higher-level process-level parallelism and task-level parallelism has become an inevitable trend to continuously improve processor performance. The advanced architecture represented by multi-core processors has become the dominant design structure in the field of high-performance computing. At present, ...

AI Technical Summary

Problems solved by technology

However, when accessing data in the memory across clusters, multiple read and write operations are required, and the NoC is also required to move the stored data, resulting in a large network time delay.

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