Method for manufacturing split-gate flash memory device

Abstract

The present invention provides a method for manufacturing a split-gate flash memory device. When etching the first sidewall material to expose the floating gate polysilicon layer at the bottom of the sidewall opening, a certain thickness on the surface of the floating gate dielectric layer is reserved The first sidewall material, and then use the remaining first sidewall material as a mask to etch the floating gate polysilicon layer and the floating gate oxide layer in the sidewall openings, so that the floating gate dielectric layer can remain on the surface of the floating gate dielectric layer A certain thickness of the first sidewall material can form the second sidewall, which can completely avoid the influence of the height of the first sidewall material on the sidewall of the floating gate dielectric layer when the second sidewall is formed, and then remove the floating gate The first spacer material remaining above the dielectric layer is used to form the final floating gate spacer, thereby ensuring the height uniformity of the floating gate spacer in the entire device area, thereby improving the programming crosstalk failure problem of the flash memory device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a split-gate flash memory device. Background technique [0002] Flash memory, referred to as flash memory, is divided into two types: stackgate (stackgate) device and split gate (splitgate) device, wherein, the split gate device forms a word line as an erasing gate on one side of the floating gate, and the word line The line is used as the control gate. In terms of erasing and writing performance, the split-gate device effectively avoids the over-erasing effect of the stacked gate device, and the circuit design is relatively simple. Moreover, the split-gate structure utilizes hot electron injection at the source end for programming, which has higher programming efficiency, and thus is widely used in various electronic products such as smart cards, SIM cards, microcontrollers, and mobile phones. [0003] Please refer to Figure 1A , Figure 1A...

AI Technical Summary

Problems solved by technology

The above-mentioned process is not only an operation on a memory cell area on the semiconductor substrate 10 (ie, a wafer substrate), but also a simultaneous processing of the memory cell areas in the memory cell array area on the semiconductor substrate 10, but the above-mentioned There are following two defects in the process: one is that in the process of etching the first sidewall material 15 to form the first sidewall 151, the central region and the edge region of the memory cell array region (i.e. the central device region and the semiconductor substrate 10 edge device region) there is a difference in etching uniformity, resulting in the final height of the first sidewall 151 formed in the edge region is lower than the height of the first sidewall 151 formed in the central region, for example, two regions in a manufactured flash memory chip product The height difference of the first side wall 151 is Left and right; Second, in the process of etching the second sidewall material to form the second sidewall 152, a certain amount of loss will be generated on the first sidewall 151, which further affects the height uniformity of the first sidewall 151 in the central area and the edge area , which eventually lead to serious program crosstalk failure problems in the edge area of ​​the wafer

Images