D-type flip-flop and its signal transmission method

Abstract

The present invention discloses a D-type flip-flop and a signal transmission method thereof. The D-type flip-flop comprises a time-delay inversion unit In, a first phase inverter I4, a first PMOS transistor M1, a second PMOS transistor M2, a first NMOS transistor M3, a second NMOS transistor M4, a third NMOS transistor M5 and a fourth NMOS transistor M6; the time-delay inversion unit In is used for outputting delayed reverse clock signals; the input end of the first inverter I4 is connected with the input end of data signals; the drain of the first NMOS transistor M3 and the drain of the first PMOS transistor M1 are connected at a first node; the drain of the second NMOS transistor M4 and the drain of the second PMOS transistor M2 are connected at a second node; the gate of the second NMOS transistor M4 is connected with the gate of the first NMOS transistor M3 and receives the clock signals; the source of the third NMOS transistor M5 is connected with the input end of the first phase inverter I4; and the gate of the fourth NMOS transistor M6 is connected with the third NMOS transistor M5 and is connected with the output end of the time-delay inversion unit In. With the D-type flip-flop and the signal transmission method thereof of the invention adopted, the technical problem that layout area is increased with the shortening of a clock period in the prior art can be solved.

Description

technical field [0001] The present application relates to the field of semiconductors, in particular, to a D-type flip-flop and a signal transmission method thereof. Background technique [0002] Such as figure 1 As shown, it is a data transmission path. The data signal D1 enters the flip-flop DFF1 on the falling edge of the clock, and then triggers the flip-flop DFF1 on the rising edge of the clock. The data signal D1 must be transmitted to the output Q1 of the flip-flop DFF1, and then arrives through the combinational logic. Flip-flop DFF2, and is established before the rising edge of the next clock arrives. The data signal can be transmitted after the data transmission path is established, therefore, the clock cycle must satisfy: T≥t cq1 +t logic +t setup2 , where t cq1 Indicates the time from the clock signal clk to Q1 in the first flip-flop DFF1, t logic is the propagation delay of combinational logic between two flip-flops, t setup2 Indicates the setup time of t...

AI Technical Summary

Problems solved by technology

[0006] The embodiment of the present application provides a D-type flip-flop and its signal transmission method to at least solve the technical problem of increasing the layout area while shortening the clock period in the prior art

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