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FPGA oriented multi-way universal configuration loading control system and method

A control system and generalized technology, applied in CAD circuit design, special data processing applications, instruments, etc., can solve the problems of low loading rate, large application limitations, inability to realize FPGA on-orbit dynamic configuration and self-refresh, etc. Simplify hardware conditions, reduce limitations, achieve real-time configuration loading and self-refresh control effects

Inactive Publication Date: 2017-05-17
XIAN MICROELECTRONICS TECH INST
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, the configuration method based on the control system and memory only controls a single FPGA to be loaded for a specific memory. The configuration loading file can only be programmed into the memory through a dedicated downloader on the ground. By controlling the reading of the configuration file in the memory, the FPGA is loaded. Configuration loading, FPGA in-orbit dynamic configuration and self-refresh cannot be realized, the loading rate is generally low, and the application limitations are relatively large

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  • FPGA oriented multi-way universal configuration loading control system and method
  • FPGA oriented multi-way universal configuration loading control system and method
  • FPGA oriented multi-way universal configuration loading control system and method

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Embodiment Construction

[0032] The present invention will be further described below in conjunction with the accompanying drawings.

[0033] see figure 1 , an FPGA-oriented multi-channel generalized configuration loading control system, comprising a host interface selection module, a frame analysis module, a register configuration module, a memory control module and an FPGA loading control module. The host interface selection module is connected uplink with the download host interface and the host computer interface, and downlink with the frame analysis module, the frame analysis module is connected with the memory control module, the memory control module is connected with the FPGA loading control module, the memory controller module, and the FPGA loading control module And the frame analysis module is connected with the register module, the memory controller module is connected with a plurality of memories, and the FPGA loading control module is connected with a plurality of FPGAs.

[0034] The ho...

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Abstract

The invention discloses a FPGA oriented multi-way universal configuration loading control system and method. The system comprises a host machine interface, a host machine interface selection module, a frame resolution module, a register configuration module, a memory control module and a FGFA loading control module. Through the interlinking interactive signals, multiple modules complete the configuration loading control work of the whole system to achieve two configuration loading modes including that the memory configures the FPGA and the host machine directly configure FPGA. Real time configuration loading and self-refreshing control of on-orbit platforms is achieved. The interface compatibility control is carried out to the ground platform and on-orbit applications to achieve access control interfaces for different application environments, and enhance the environmental adaptability of a product.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to an FPGA-oriented multi-channel generalized configuration loading control system and method. Background technique [0002] With the continuous development of microelectronics technology, FPGA is widely used in the development and debugging stages of electronic circuits and systems. FPGA can support repeated programming, but the data disappears after power-off, and it needs to be reloaded every time it is powered on. Currently, there are two commonly used FPGA configuration loading methods: 1) FPGA is loaded in JTAG mode, using a dedicated software and hardware downloader to load the configuration file into the FPGA through the JTAG download port, this method is only applicable to the development and debugging stages . If the FPGA does not load the environment or use different configuration files, this configuration method is difficult to meet the environment ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/34G06F30/39
Inventor 张春妹李磊张洵颖裴茹霞
Owner XIAN MICROELECTRONICS TECH INST
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