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Chip achieving method of PVLAN in stacked mode

An implementation method and chip technology, applied in the direction of network interconnection, data exchange through path configuration, etc., to achieve the effects of reducing the number of devices, expanding the application range, flexible and efficient applications

Active Publication Date: 2017-05-17
SUZHOU CENTEC COMM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] But at this stage there is no technical solution to realize PVLAN in stacking mode

Method used

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  • Chip achieving method of PVLAN in stacked mode
  • Chip achieving method of PVLAN in stacked mode
  • Chip achieving method of PVLAN in stacked mode

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 2

[0089] The difference between Embodiment 2 and Embodiment 1 is that the outgoing direction isolation label information of ports is configured globally, that is, each chip participating in the stack has the isolation label information of the outgoing direction of the ports of all chips participating in the stacking. In this way, the PVLAN forwarding rule inspection implemented by port isolation can be performed on the ingress chip to know whether to discard the packet. If discarded, the discarding action is performed on the ingress chip instead of the egress chip to perform discarding, which can reduce the aggregation (stacking) port bandwidth pressure.

[0090] The configuration of the first isolation label, the second isolation label, and the forwarding rules of PVLAN in this scheme is the same as that in the above-mentioned embodiment 1, and the processing of the message is also carried out correspondingly according to the forwarding rules of PVLAN. For the specific configura...

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Abstract

The invention discloses a chip achieving method of a PVLAN in a stacked mode. A corresponding VLAN, a first isolating mark number in the output direction and a second isolating mark number in the input direction are distributed to a port of a stacked chip, a forwarding rule of the PVLAN is configured in the stacked chip, after the chip receives a message, the message is processed according to the forwarding rule of the PVLAN, that is, communication is carried out according to the attribute of the PVLAN, and information of the PVLAN can be transmitted in a cross-chip mode. The application range of the PVLAN technology is greatly widened, and application of the PVLAN is more flexible and efficient.

Description

technical field [0001] The invention relates to a PVLAN (Private VLAN, dedicated virtual local area network) technology, in particular to a chip implementation method of PVLAN in a stacking mode. Background technique [0002] Stacking technology is a common technology for extending ports on Ethernet switches, which can be stacking at the switch level or at the switching chip level. The switches (switching chips) participating in the stack are connected through topologies such as ring (ring), tree (tree), and fullmesh (full mesh), and are regarded as one device on the management plane. [0003] PVLAN is a technology used to solve the effective allocation and rational utilization of VLAN (Virtual Local Area Network) resources in the operator network. The basic principle of this technology is to assign two different attributes to the VLAN, namely Primary VLAN VLAN for operating network communication) and Secondary VLAN (auxiliary VLAN, VLAN for communicating with users), where...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/46
CPCH04L12/4641H04L12/4675
Inventor 张国颖杨曙军单哲
Owner SUZHOU CENTEC COMM CO LTD