A high-speed dac circuit and its calibration method

Abstract

The present invention discloses a high-speed digital to analog converter (DAC) circuit and a correction method thereof. The correction method comprises the steps of turning on a correction channel switch, entering a correction mode, and inputting the same digital signal to each signal channel; detecting, by a correction unit, input signals of a current source switch array, using any input signal as a reference signal, using input signals of other signal channels as to-be-corrected signals, generating a correction signal according to asynchronous digital signals through comparison and determining, and sending the correction signal to a corresponding adjustable delay drive unit; performing delay adjustment on the asynchronous digital signals according to the correction signal; and after correction is finished, turning off the correction channel switch, entering a working mode, and driving, by the adjustable delay drive unit, the current source switch array to perform digital to analog conversion. Through adoption of the correction method, multiple signals of the high-speed DAC chip do not have time difference, output glitch of the high-speed DAC circuit is greatly reduced, the dynamic characteristic of the high-speed DAC circuit is improved, and the performance of the high-speed DAC chip is optimized.

Description

technical field [0001] The invention relates to the technical field of high-speed DAC (Digital to Analog Converter, digital-to-analog converter) circuit design, in particular to a high-speed DAC circuit and a calibration method thereof. Background technique [0002] With the rapid development of communication technology, communication networks have higher and higher requirements for chip performance. The performance of high-speed DAC chips has become one of the bottlenecks restricting the development of future communication technology. How to improve the performance of high-speed DAC chips is a difficult point in the research field. . [0003] Signal time difference is one of the main reasons affecting the performance of high-speed DAC chips. In the DAC circuit of high-speed DAC chips, digital signals are converted into analog signals through current source switch arrays. Digital signal time differences will cause glitches in the output and affect the output of high-speed DA...

AI Technical Summary

Problems solved by technology

[0004] In high-speed DAC chips, especially segmented current steering DAC chips, the signal time difference reaching PS level has a relatively large impact on chip performance. The method of using D flip-flops and layout optimization has certain limitations. The specific performance is: high and low Differences in switch drive and layout will cause signal time difference, the weight of the high position is heavy, and the load of the driven switch is large, resulting in a greater delay of the high level signal than the low level signal, resulting in multi-channel signal time difference

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