Terminal equipment, reading and writing equipment, data transmission system and hardware initializing method

[0041] Example one

[0042] Figure 1a This is a structural diagram of a terminal device provided in Embodiment 1 of the present invention. The structure of the terminal device in this embodiment specifically includes:

[0043] A first universal serial bus interface 110, an upstream port 150, a downstream port 160, a switch 170, a first controller 140, and a first switch circuit 130;

[0044] The first universal serial bus interface 110 is used to connect to the universal serial bus interface of an external device, and its signal pin is grounded; both the upstream port 150 and the downstream port 160 are connected to the first universal serial bus interface 110 through the switch 170 The data transmission end of the first switch circuit 130 is connected, and the on-off state is switched through the switch 170; the first end of the first switch circuit 130 is connected to the power pin of the first universal serial bus interface 110, and the second end of the first switch circuit 130 is connected Input power, generally 5V system power, namely System 5V;

[0045] The first control terminal of the first controller 140 is connected to the controlled terminal of the switch 170, and the signal Switch CTL is sent to control the switch 170 to switch between the upstream port and the downstream port; the second control terminal of the first controller 140 is connected to the The controlled end of a switch circuit 130 is connected, and a signal 5V_CTL is sent to control the on and off of the first switch circuit 130; the signal input end of the first controller 140 is connected to the voltage detection data of the power pin of the first universal serial bus interface 110 , And send signals Switch CTL and 5V_CTL to the switch 170 and the first switch circuit 130 according to the voltage detection data.

[0046] Further, such as Figure 1b As shown, the first switch circuit 130 is optimized to include a resistor R3, a resistor R4, a resistor R5, a transistor Q2, and a MOS transistor Q1; the first end of the resistor R3 is connected to the second control end of the first controller 140 for Receive the signal 5V_CTL; the second end of the resistor R3 is connected to the base of the transistor Q2; the emitter of the transistor Q2 is grounded, the collector of the transistor Q2 is connected to the first end of the resistor R4 and the first end of the resistor R5; the second end of the resistor R4 The two ends are connected to the source of the MOS transistor Q1 and connected to the power supply System 5V; the second end of the resistor R5 is connected to the gate of the MOS transistor Q1; the drain of the MOS transistor Q1 is connected to the second end of the current limiting circuit 120, For receiving power VCC_out.

[0047] Such as Figure 1a with Figure 1b As shown, when the terminal device is in the initial state, the second control terminal output signal 5V_CTL of the first controller 140 is at a high level, so that the controlled terminal input of the first switch circuit 130 is at a high level, that is, the first control terminal of the resistor R3 One end of the input is high, so that the transistor Q2 is turned on. At the same time, the second end of the resistor R4 is connected to the power supply System 5V, so that the MOS transistor Q1 is turned on, so that the connected power supply System 5V from Q1 through the MOS transistor Q1 The drain is output to the power supply pin of the first universal serial bus interface 110.

[0048] Since the input of the power pin of the first universal serial bus interface 110 is high level System 5V, that is, the voltage detection data of the power pin of the first universal serial bus interface 110 is high level, in this embodiment, The voltage detection data of the power pin of the first universal serial bus interface 110 is defined as 5V Det. Therefore, the signal 5V Det input from the signal input terminal of the first controller 140 is at a high level, and when the first controller 140 detects When the input signal 5V Det is at a high level, the first controller 140 controls the switch 170 to switch to the downstream port 160 through the output control signal Switch CTL from the first control terminal, so that the data transmission terminal of the first universal serial bus interface 110 is connected to Downstream port 160.

[0049] Figure 1c Shown is a device 310 that uses a universal serial bus interface as an upstream port, where the shell and signal pins of the universal serial bus interface are grounded. when Figure 1c Universal serial bus interface in Figure 1a After the first universal serial bus interface 110 in the Figure 1a There will be no changes in the internal terminal equipment, continue to maintain the initial state, and can be Figure 1c The device using the universal serial bus interface as the uplink port communicates normally for data transmission.

[0050] There is another situation, when the terminal device in this embodiment needs to be read by other devices, Figure 1a After the first universal serial bus interface 110 is inserted into the universal serial bus interface of the dedicated reading device, the power pin of the first universal serial bus interface 110 is grounded, so that the input signal of the first controller 140 is 5V Det When the first controller 140 detects that the input signal 5V Det becomes 0, the first controller 140 changes the output signal 5V_CTL to 0, and then the input of the controlled terminal of the first switch circuit 130 becomes 0, resulting in a triode Q2 is turned off, and then the MOS transistor Q1 is turned off, and the power System 5V connected to the resistor R4 cannot be output to the power supply pin of the first universal serial bus interface 110 through the MOS transistor Q1. After the first controller 140 detects that the input signal 5V Det becomes 0, it will also control the switch 170 to switch to the upstream port 150, thus completing the first universal serial bus interface 110 from the downstream port to the upstream port. change.

[0051] It should be noted here that, in this embodiment and all subsequent embodiments, the downlink port specifically refers to another universal serial port that is connected to it during data transmission through the universal serial bus interface. The bus interface provides power and plays a leading role in the process of data transmission. Correspondingly, the above-mentioned "another universal serial bus interface" is the uplink port. In other words, the so-called "uplink" and "downlink" here do not refer to the direction of data flow during data transmission, but refer to the difference in the master-slave status of the two universal serial bus interfaces during data transmission. Name it.

[0052] The terminal device provided by the embodiment of the present invention configures circuit components such as the first universal serial bus interface 110, the upstream port 150, the downstream port 160, the switch 170, the first controller 140, and the first switch circuit 130 in the terminal device. , So that the first universal serial bus interface 110 can be multiplexed as the downlink port 160 or the uplink port 150, which solves the problem that no matter what kind of failure occurs in the device equipped with the universal serial bus interface in the prior art, the internal data cannot pass through The technical problem of universal serial bus interface connection being read, realizes that when a device configured with universal serial bus interface is connected to an external device through a universal serial bus interface, the external device can actively read the configuration with universal serial bus The internal data of the device of the interface.

[0053] Example two

[0054] The second embodiment of the present invention provides a structural diagram of a terminal device. This embodiment is optimized on the basis of the above embodiment. In this embodiment, as figure 2 As shown, it further includes: a current-limiting circuit 120. The first end of the current-limiting circuit 120 is connected to the power supply pin of the first universal serial bus interface 110 (that is, the pin that outputs or connects to +5V), and the current-limiting circuit 120 The third terminal of is connected to the signal input terminal of the first controller 140 for outputting a signal of 5V Det, and the second terminal of the current limiting circuit 120 is connected to the first terminal of the first switch circuit 130;

[0055] Further, the current-limiting circuit 120 is optimized to include a current-limiting switch 180, a resistor R1, and a resistor R2; the first end of the current-limiting switch 180, the first end of the resistor R1, and the power source of the first universal serial bus interface 110 Pin connected to the power pin of the first universal serial bus interface 110 to output the power supply voltage USB5V, the second end of the current-limiting switch 180 is connected to the first end of the first switch circuit 130; the second end of the resistor R1 is connected to the The first end of the resistor R2 is connected to the signal input end of the first controller 140; the second end of the resistor R2 is grounded.

[0056] Such as figure 2 As shown, also, when the terminal device is in the initial state, the second control terminal output signal 5V_CTL of the first controller 140 is high, so that the controlled terminal input of the first switch circuit 130 is high, that is, the resistor R3 The first end of the input is high level, so that the transistor Q2 is turned on, and at the same time, the second end of the resistor R4 is connected to the power supply System 5V, so that the MOS transistor Q1 is turned on, and then the connected power supply System 5V is from the MOS transistor Q1 The drain of Q1 is output to the second terminal of the current limiting circuit 120, that is, the second terminal of the current limiting switch 180.

[0057] After the second end of the current-limiting switch 180 is connected to the power supply System 5V output by the drain of the MOS transistor Q1, the System 5V is output to the power supply pin of the first universal serial bus interface 110 through the current-limiting switch 180. At the same time, System 5V The resistor R1 and the resistor R2 are grounded, so that the second end of the resistor R1 (connected to the first end of the resistor R2) presents a high level. Therefore, the input signal 5V Det of the first controller 140 is a high level. When the first controller 140 detects that the input signal 5V Det is at a high level, the first controller 140 outputs a control signal Switch CTL through the first control terminal to control the switch 170 to switch to the downstream port 160, so that the first universal serial bus interface 110 The data transmission end of is connected to the downstream port 160.

[0058] when Figure 1c Insert the device 310 in the Universal Serial Bus interface as the upstream port figure 2 After the first universal serial bus interface 110 in the figure 2 There will be no changes in the internal terminal equipment, continue to maintain the initial state, and can be Figure 1c The device using the universal serial bus interface as the uplink port communicates normally for data transmission.

[0059] There is another situation, when the terminal device in this embodiment needs to be read by other devices, figure 2 After the first universal serial bus interface 110 is inserted into the universal serial bus interface of the dedicated reading device, the power supply pin of the first universal serial bus interface 110 is grounded, and then triggers figure 2 In the current-limiting switch 180, the first terminal output of the current-limiting switch 180 is 0, that is, the first terminal input of the resistor R1 is 0. Therefore, the input signal 5V Det of the first controller 140 is 0. When the first control After the detector 140 detects that the input signal 5V Det becomes 0, the first controller 140 changes the output signal 5V_CTL to 0, and then the input of the controlled terminal of the first switch circuit 130 becomes 0, causing the transistor Q2 to turn off, and the MOS transistor Q1 When turned off, the power System 5V connected to the resistor R4 cannot be output to the second end of the current limiting circuit 120 through the MOS transistor Q1. After the first controller 140 detects that the input signal 5V Det becomes 0, it will also control the switch 170 to switch to the upstream port 150, thus completing the first universal serial bus interface 110 from the downstream port to the upstream port. change. The function of the current-limiting switch 180 is to automatically turn off the current-limiting switch when the current passing through the current-limiting switch is greater than a preset threshold, so that the circuits at both ends of the current-limiting switch are disconnected. Since the current-limiting switch belongs to the prior art, it will not be elaborated here.

[0060] The terminal device provided by the embodiment of the present invention configures the first universal serial bus interface 110, the upstream port 150, the downstream port 160, the switch 170, the first controller 140, the current limiting circuit 120 and the first switch in the terminal device. Circuit 130 and other circuit devices, so that the first universal serial bus interface 110 can be multiplexed as a downstream port 160 or an upstream port 150, which solves the problem of any failure of the device equipped with the universal serial bus interface in the prior art. The data can not be read through the universal serial bus interface connection. It is realized that when a device configured with a universal serial bus interface is connected to an external device through a universal serial bus interface, the external device can actively read the configuration Internal data of devices with universal serial bus interface.

[0061] Example three

[0062] Figure 3a This is a structural diagram of a read-write device provided in Embodiment 3 of the present invention, which specifically includes:

[0063] The second universal serial bus interface 230, the second controller 250, the trigger circuit 240, the second switch circuit 210, and the third switch circuit 220; the signal pin Signal_GND of the second universal serial bus interface 230 and the trigger The detection terminal of the circuit 240 is connected, and the feedback terminal of the trigger circuit 240 is connected with the signal input terminal of the second controller 250. In this embodiment, the signal transmitted between the two is defined as Insert Det, which is specifically used for Describe the voltage state of the second universal serial bus interface 230;

[0064] The signal pins of the second universal serial bus interface 230 are used to connect with the signal pins of the first universal serial bus interface 110; the data processing end of the second controller 250 and the second universal serial bus interface 230 are used for data transmission Terminal connected to read and write data through the second universal serial bus interface 230; the first control terminal of the second controller 250 is connected to the controlled terminal of the second switch circuit 210, and the signal ON/OFF_CTL is sent to control the second switch circuit 210 On and off; the second control terminal of the second controller 250 is connected to the controlled terminal of the third switch circuit 220, and sends a signal CTL to control the on and off of the third switch circuit 220, and the second controller 250 decides to be ON according to the signal Insert Det /OFF_CTL and CTL specific control content; the first end of the second switch circuit 210 is connected to +5V power, the second end of the second switch circuit 210 is connected to the power supply pin of the second universal serial bus interface 230 (that is, output or The +5V pin) is connected, and the power supply VCC_out' is output to the power supply pin of the second universal serial bus interface 230; the first end of the third switch circuit 220 is connected to the power supply lead of the second universal serial bus interface 230 The pins are connected, and the second end of the third switch circuit 220 is grounded.

[0065] Further, the trigger circuit 240 is optimized to include a transistor Q3, a resistor R6, a resistor R7, and a resistor R8. The first end of the resistor R6 is connected to the signal pin of the second universal serial bus interface 230; the second end of the resistor R6 Connected to the base of the transistor Q3 and the first end of the resistor R7; the second end of the resistor R7 is connected to the first end of the resistor R8 and connected to the +5V voltage; the second end of the resistor R8 is connected to the collector of the transistor Q3 and the first end The signal input terminals of the second controller 250 are connected to output the signal Insert Det; the emitter of the transistor Q3 is grounded.

[0066] Further, the second switch circuit 210 is optimized to include a resistor R9, a resistor R10, a resistor R11, a transistor Q4, and a MOS transistor Q5; the first terminal of the resistor R9 is connected to the first control terminal of the second controller 250 for Receive ON/OFF_CTL; the second end of resistor R9 is connected to the base of transistor Q4; the emitter of transistor Q4 is grounded, and the collector of transistor Q4 is connected to the first end of resistor R10 and the first end of resistor R11; The second end is connected to the source of the MOS transistor Q5 and connected to the power supply; the second end of the resistor R11 is connected to the gate of the MOS transistor Q5; the drain of the MOS transistor Q5 is connected to the power supply pin of the USB male port 230 to connect the power supply VCC_out' is output to the power supply pin.

[0067] Further, the third switch circuit 220 is optimized to include a resistor R13, a resistor R12, and a transistor Q6; the first end of the resistor R13 is connected to the second control end of the second controller 250 for outputting the CTL to the resistor R13 At the first end, the second end of resistor R13 is connected to the base of transistor Q6; the emitter of transistor Q6 is grounded, the collector of transistor Q6 is connected to the first end of resistor R12, and the second end of resistor R12 is connected to the second universal string The power pins of the row bus interface 230 are connected.

[0068] In this embodiment, Figure 3a The initial state of the read-write device in is that the ON/OFF_CTL and CTL output by the first control terminal and the second control terminal of the second controller 250 are both low level. Such as Figure 3b As shown, since the first control terminal output ON/OFF_CTL of the second controller 250 is low level, the first terminal input of the resistor R9 is low level, and then the transistor Q4 is turned off, and the MOS transistor Q5 is also turned off, namely Q5 The drain of the second universal serial bus interface 230 has no voltage output, so the power pin of the second universal serial bus interface 230 has no voltage input. Such as Figure 3a As shown, the CTL output by the second control terminal of the second controller 250 is low, therefore, the first terminal input of the resistor R13 is low, and the transistor Q6 is turned off. Such as Figure 3a As shown, a +5V power supply is connected to the trigger circuit 240, which turns on the transistor Q3, and the collector of Q3 presents a low level. Therefore, the second controller 250 inputs Insert Det to a low level.

[0069] The read-write device in this embodiment uses the second universal serial bus interface 230 as an external port, and a trigger circuit 240 is set in the second universal serial bus interface 230, when it is necessary to set a universal serial bus interface from an unconventional When reading data from a storage device (such as a terminal device), the trigger circuit 240 and multiple switch circuits inside the read-write device realize the establishment of a data channel based on the universal serial bus interface. Read data from the storage device.