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Improving lateral BJT characteristics in BCD technology

A horizontal and collector technology, applied in the direction of semiconductor devices, electrical components, transistors, etc., can solve the problem of insufficient height

Active Publication Date: 2017-08-18
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] BV of this device CEO Limited by Pepi-SNW or Pepi-DEEPN junction breakdown and usually not high enough for device operation

Method used

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  • Improving lateral BJT characteristics in BCD technology
  • Improving lateral BJT characteristics in BCD technology
  • Improving lateral BJT characteristics in BCD technology

Examples

Experimental program
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Embodiment Construction

[0016] In an example embodiment, a CMOS / DMOS fabrication process allows optimization of bipolar transistor parameters, including those related to horizontal bipolar transistors, without significantly increasing the number of steps and / or masks required in the process.

[0017] image 3 and 4 An example embodiment of a BiCMOS structure defining vertical and lateral NPN bipolar junction transistors (BJTs) is shown. In other examples, the structure can also be implemented to define lateral PNPs by using opposite polarities of the various doped regions.

[0018] Such as image 3 The structure is formed on a p-substrate (PSub) 300 as shown in the cross-sectional side view of . The emitters of both the vertical and lateral NPN bipolar transistors are bounded by n-type source-drain (NSD) regions 310 . The base is formed by p epitaxial region (Pepi) 312 and p buried layer (PBLMV) 314 . In the case of a lateral BJT, contact to Pepi 312 defining the base is made by a p-type source dr...

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Abstract

In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BVCEO) and BJT's gain, are improved by forming a graded collector contact region (320) with lower doping levels toward the base contact (340).

Description

technical field [0001] The present invention relates generally to the fabrication of semiconductor devices, and more particularly to BiCMOS devices and improving lateral BJT characteristics. Background technique [0002] Integrated circuits having bipolar and MOS transistors formed on the same semiconductor substrate have many applications in the electronics industry, and therefore, there is a great demand for integrated circuits. Integrated circuits combine the high power and fast switching speed of bipolar devices with the high density and low power consumption of MOS transistors. [0003] When forming devices using a Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) fabrication process, care is taken to minimize the number of masks employed in the process in order to reduce fabrication costs. Therefore, whenever feasible, efforts have been made to integrate the use of areas normally used by CMOS / DMOS devices into areas in bipolar devices, and vice versa. In BCD (...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331H01L29/73
CPCH01L21/8249H01L27/0623H01L29/0692H01L29/0821H01L29/66272H01L29/732H01L29/6625H01L29/735
Inventor 纳塔莉娅·拉夫洛夫斯卡娅阿列克谢·萨多夫尼科夫
Owner TEXAS INSTR INC