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Semiconductor Structure And Fabricating Method Thereof

A semiconductor and conductive layer technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems affecting the quality of bump connections

Inactive Publication Date: 2017-10-03
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some factors in the manufacturing process, such as delamination and corrosion problems, may affect the quality of the bump connection

Method used

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  • Semiconductor Structure And Fabricating Method Thereof
  • Semiconductor Structure And Fabricating Method Thereof
  • Semiconductor Structure And Fabricating Method Thereof

Examples

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Embodiment Construction

[0009] The present disclosure provides several different implementation methods or embodiments, which can be used to realize different features of the present disclosure. For simplicity of illustration, the present disclosure also describes examples of certain components and arrangements. Please note that these specific examples are provided for illustration purposes only and are not intended to be limiting. For example, the following description of how a first feature is on or over a second feature may include embodiments where the first feature is in direct contact with the second feature, and the description may also include other differences. An embodiment wherein there is another feature between the first feature and the second feature such that the first feature is not in direct contact with the second feature. In addition, various examples in this disclosure may use repeated reference numerals and / or text notations to simplify and clarify the document, and these repeat...

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Abstract

A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof. Background technique [0002] Electronic devices are now central to many modern applications. As a result, consumers are increasingly demanding higher processing power, lower power usage, and less expensive devices. As the electronics industry grapples with these demands and more complex and denser architectures, miniaturization will result in an increase in the number of chips per wafer and transistors per chip, as well as lower power usage. Wafer level packaging (WLP) technology has become increasingly popular as electronic components are designed to be lighter, smaller, more functional, more powerful, more reliable and less expensive. WLP technology combines bare chips with different functions at the wafer level, and is widely used to meet the continuous demand for miniaturization and higher functions of electronic components. [0003] Typ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/488
CPCH01L24/11H01L24/13H01L2224/1161H01L24/03H01L24/05H01L2224/131H01L2224/03462H01L2224/0347H01L2224/0391H01L2924/35121H01L2224/05569H01L21/02071H01L21/3105H01L21/31058H01L23/3192H01L2224/03632H01L2224/0345H01L2224/03452H01L2224/03464H01L2224/0361H01L2224/0362H01L2224/05008H01L2224/05147H01L2224/05166H01L2224/05599H01L2224/05572H01L2224/0239H01L2224/0381H01L2224/0401H01L2924/00014H01L2924/01022H01L2924/013H01L21/02334H01L24/02H01L2224/02235H01L2224/02251H01L2224/02255H01L2224/02311H01L2224/02313H01L2224/0236H01L2924/01029H01L2924/0132H01L24/42
Inventor 黄伟立翁正杰苏祥盛黄宗隆刘国洲黄信傑廖德堆古进誉陈承先
Owner TAIWAN SEMICON MFG CO LTD