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A ferroelectric ingazno non-volatile memory with double gate structure

A non-volatile, double-gate structure technology, applied in the direction of electric solid-state devices, circuits, electrical components, etc., can solve the problems of increasing device power consumption, deteriorating ferroelectric layer performance, reducing memory reliability, etc., to achieve enhanced storage performance , Eliminate stress effects and improve reliability

Active Publication Date: 2019-11-08
SOUTHEAST UNIV
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  • Application Information

AI Technical Summary

Problems solved by technology

By increasing the "program / erase (Program / Erase, P / E)" voltage, the storage window of the memory can be increased; on the other hand, the stress generated by the large "program / erase" voltage will deteriorate the reliability of the memory and will increase the power consumption of the device
In addition, for the existing ferroelectric NVM, the operations of "programming / erasing" (realizing information storage) and "reading" (realizing information reading) are usually performed using the same gate. Therefore, when performing "reading" operations, The stress generated by the "read" operating voltage applied to the gate will deteriorate the performance of the ferroelectric layer, thereby reducing the reliability of the memory

Method used

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  • A ferroelectric ingazno non-volatile memory with double gate structure
  • A ferroelectric ingazno non-volatile memory with double gate structure

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Embodiment Construction

[0014] Such as figure 1 As shown, a ferroelectric InGaZnO nonvolatile memory with double gate structure includes a substrate 10, a bottom gate 11 disposed on the substrate 10, a bottom gate oxide disposed on the substrate 10 and covering the bottom gate 11 layer 12, the InGaZnO channel layer 13 arranged on the bottom gate oxide layer 12, the source electrode 14 and the drain electrode 15 arranged on the opposite sides of the InGaZnO channel layer 13, the source electrode 14 arranged on the InGaZnO channel layer 13 and the source electrode 14 , the ferroelectric layer 16 on the drain 15 , the top gate 17 disposed on the ferroelectric layer 16 , the top gate 17 is located directly above the bottom gate 11 . The equivalent oxide thickness T of the bottom gate oxide layer 12 BOX , the equivalent oxide layer thickness T of the InGaZnO channel layer 13 IGZO and the equivalent oxide thickness T of the ferroelectric layer 16 TOX Satisfied: 3>T BOX / (T TOX +T IGZO )>1.

[0015] ...

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Abstract

The invention discloses a ferroelectric InGaZnO nonvolatile memory with a double gate structure, which is: top gate / ferroelectric layer / channel layer / bottom gate oxide layer / bottom gate from top to bottom. The non-volatile memory improves the storage window and reliability of the memory by separating the "program / erase" and "read" operations in structure.

Description

technical field [0001] The invention relates to the field of semiconductor nonvolatile memory, in particular to a ferroelectric InGaZnO nonvolatile memory with double gate structure. Background technique [0002] Flat panel displays have been widely used in various electronic products such as TVs, computers, and smart phones, and have greatly improved people's lives. With the rapid increase of people's demand for higher-quality products such as low-power and high-resolution portable electronic devices and large-size 3D displays, researchers have proposed the "System on Panel (SoP)" technology, which puts Modules with different functions (such as pixel circuits, peripheral drive circuits, and information storage modules) are integrated on the panel. SoP technology significantly improves product stability and working speed while reducing product cost and power consumption, so it is a beneficial technical way to develop high-quality flat panel displays. Thin Film Transistor (...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11585H01L29/78
CPCH01L29/78391H10B51/00
Inventor 黄晓东黄见秋
Owner SOUTHEAST UNIV